MC68020 Assembler - Ver 2.88 14-Dec-88 Page 1 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement ;------------------------------------------------------------------- ; ; (c) Apple Computer, Inc. 1987 ; All rights reserved. ; ;------------------------------------------------------------------- ; ; File : CommROM.a ; Author : Michael Klassen, June 8, 1987. ; Description : This file contains the data structure definition ; for the MCP Comm Engine card. ; ;------------------------------------------------------------------- ; Modification History : ; ; 7 March 1988: WHJW: mods to support multiple ROM vers w/ same source code ; 8 July 1988: WHJW: Correctly identified slot resource list entries ;------------------------------------------------------------------- ;************************************************************* ;Constants ;************************************************************* INCLUDE 'CommDeclr.h' ;************************************************************************* ; ; CommDeclr.h: ; Constants used for Smart card Diagnostics 0007 FFFE STACK EQU $7FFFE ; offset of stack in card RAM 0001 0000 ROMSize EQU (64*1024) ; ROM = 64K 0000 0000 OFF equ 0 FFFF FFFF ON equ -1 0000 0000 PASS equ 0 FFFF FFFF FAIL equ -1 0000 0001 WAIT equ 1 ; Delay constants in microseconds 0000 0D00 TimeDBRA equ $D00 ; (word) location: # of DBRA instructions/mSecond 0000 01F4 WaitCount equ 500 ; timeout - wait for power_on finish 0000 0004 TimeCnt equ 4 ; timeout for IOP test 0000 0010 TimerWait equ 16 ; timeout for Timer test 0000 0004 Delay equ 4 ; Reset delay ; variable offsets into card RAM 0000 0100 WaitFlag equ $100 ; power_on wait flag 0000 0102 TstStatus equ $102 ; test status bit flags 0000 0104 TimeFlag equ $104 ; flag for timer test 0000 0106 HostFlag equ $106 ; flag for host reset test 0000 0108 ResetFlag equ $108 ; flag to control reset code 0000 010C IOPFlag equ $10C ; flag for IOP interrupt test 0000 010E CRCCalcAddr equ $10E ; ROM calculated CRC value 0000 0112 WriteLoc equ $112 ; Location of Nubus write/read test ;rteAddr equ $116 ; rte for interrupt vectors (no longer used) 0000 0118 timeCountAddr equ $118 ; address of firmware timer counter 0000 011C RAMSizeAddr equ $11c ; Size of card RAM in bytes 0000 0120 TASStatusAddr equ $120 ; returns test & set card status to 020 0000 0122 NMRQFlag equ $122 ; flag for NMRQ test 0000 0128 BusErrAddr equ $128 ; flag for bus error 0000 012C InitA5Addr equ $12c ; Used for finding data block 0000 0130 CodeOffset equ $130 ; Used for finding code block 0000 0134 VendPowerStatus equ $134 ; return status from vendors power-up code 0000 0138 VendPrimaryStatus equ $138 ; return status from vendors Primary init code 0000 013C ExceptionPC equ $13C ; PC stored here after exception takes place 0000 0140 ErrorAddr equ $140 ; data addr stored here after bus or addressing error 0000 0144 RAMErrAddr equ $144 ; if RAM error occurs, its address stored here 0000 0148 L1IntAddr equ $148 ; Mac processor stores new Timer interrupt loc here; ; then calls SetL1Interrupt to set it safely. ; card space to $180 to $200 reserved for temporary data values only 00E0 0000 testROMAddr equ $e00000 ; location of Fremont board tester ROM 0080 0008 ROMversion equ $800008 ; location of Mac II ROM version number ; Test status bit masks MC68020 Assembler - Ver 2.88 14-Dec-88 Page 2 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement 0000 FFFF testsDefined equ $ffff ; currently defined test bits 0000 FFFE DLTestMask equ $fffe ; sliding 5 data line test 0000 FFFD RAMTestMask equ $fffd 0000 FFFB testPatternMask equ $fffb ; signals PROM burned incorrectly 0000 FFF7 CRCTestMask equ $fff7 ; Clears CRC test bit 0000 FFEF VendPowerupMask equ $ffef 0000 001F PowerMask equ $1F FFFF FFDF BusMask equ $FFFFFFDF ; clears Nubus write/read test bit FFFF FFBF HostMask equ $FFFFFFBF ; clears host reset test bit FFFF FF7F TimeMask equ $FFFFFF7F ; clears timer test bit FFFF FEFF IOPMask equ $FFFFFEFF ; clears IOP test bit FFFF FDFF VendMask equ $FFFFFDFF ; clears vendor test bit FFFF FBFF NMRQMask equ $FFFFFBFF ; clears NMRQ test bit ; Card control switch offsets 00C0 0000 ExtReg equ $C00000 ; Nubus extension register (write) or unreset (read) 00C0 0002 TimerSet equ $C00002 ; Timer interrupt switch (read) 00C0 0008 ClrIOPIntr equ $C00008 ; Clear Interrupt IOP request (read) 00C0 000A SetIOPIntr equ $C0000A ; Set Interrupt IOP request (read) 00C0 0004 ClrHostIntr equ $C00004 ; Clear Host Interrupt request (read) 00C0 0006 SetHostIntr equ $C00006 ; Set Host Interrupt request (read) 00F0 0000 Reset equ $F00000 ; programmed reset of 68000 (write) 00B0 0000 SetTASAddr equ $B00000 ; Prime card for an offcard TAS instruction ; Pointers to interrupt test routines 00FF FF60 SetL1Addr equ $FFFF60 00FF FF80 TimeAddr equ $FFFF80 00FF FFA0 HostAddr equ $FFFFA0 00FF FFC0 IOPAddr equ $FFFFC0 ; test patterns 5555 5555 testWord1 equ $55555555 ; power-up RAM test data word AAAA AAAA testWord2 equ $aaaaaaaa 5A5A 5A5A testWord3 equ $5a5a5a5a 55AA 55AA testWord4 equ $55aa55aa 5A93 2BC7 bTestPattern equ $5a932bc7 ; test pattern in identifier block AAAA 5555 testROMSig equ $aaaa5555 ; PVT test ROM Signature ; format header block offsets 00FF FFFF fBlockLoc equ $ffffff ; 0, 1, 2, 3 bytelanes begins here 0000 0000 byteLanes equ 0 FFFF FFFB testPatLoc equ -5 FFFF FFFA formatLoc equ -6 FFFF FFF5 CRCLoc equ -$b FFFF FFF1 lengthLoc equ -$f FFFF FFEB CommIDLoc equ -$15 ;used to identify GMSIOP card application FFFF FFE9 VendIDLoc equ -$17 ;used to identify specific hardware configuration 0000 C3D2 CommID equ $c3d2 ;GMSIOP card ROM identifier 0000 0001 MacID equ 01 ; Mac II ROM ID ;Equates shared by asmlib.a & exceptions.a 0000 00F7 mode24mask equ $F7 0000 0008 mode32mask equ $8 50F0 2000 addrPort equ $50F02000 ;32 bit hardware switch; no longer accessed directly 0000 0CB2 MMU32bit equ $0CB2 ;(byte) boolean reflecting current 020 machine MMU mode 00FF FFEC codePtr equ $FFFFEC 0000 0A7C MyIntHndl equ $a7c ;handle in 020 Application scratch memory 0000 0A80 AppScratch equ $a80 ;last 4 bytes of appl scratch area A9FF _Debugger OPWORD $A9FF A11E _NewPtr OPWORD $A100+30 A01F _DisposPtr OPWORD $A000+31 A05D _SwapMMUMode OPWORD $A05D ;from traps.a A075 _SIntInstall OPWORD $A075 A076 _SIntRemove OPWORD $A076 A9F2 _Launch OPWORD $A9F2 MACRO _m32 move.l d0, -(a7) move.l #1, d0 _SwapMMUMode move.l (a7)+, d0 MC68020 Assembler - Ver 2.88 14-Dec-88 Page 3 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement ENDM MACRO _m24 move.l d0, -(a7) move.l #0, d0 _SwapMMUMode move.l (a7)+, d0 ENDM INCLUDE 'Application.h' ;================================================================================== ; File: Application.h ; ; Function: Application card ROM constants stored here ; 0042 0001 bcpRIC equ $420001 ; 8344 remote interface configuration register 0040 0001 bcpPC equ $400001 ; Dummy address for writing to 8344 PC 0040 0001 bcpDRAM equ $400001 ; 8344 Data RAM address base 0040 7C15 bcpGoodData equ $3E0A * 2 + bcpDRAM ; Test data 0040 7C17 bcpBadData equ $3E0B * 2 + bcpDRAM ; Bad data read back 0040 7C19 bcpErrAddrHi equ $3E0C * 2 + bcpDRAM ; Failed memory address, high order 0040 7C1B bcpErrAddrLo equ $3E0D * 2 + bcpDRAM ; Failed memory address, low order 0040 7C1D bcpTestErr equ $3E0E * 2 + bcpDRAM ; BCP test error bits 0040 7C1F bcpTestState equ $3E0F * 2 + bcpDRAM ; BCP test states 0040 7C01 bcpComm equ $3E00 * 2 + bcpDRAM ; BCP - 68k communication area 0040 8001 bcpDMEnd equ $4000 * 2 + bcpDRAM ; Last data memory + 1 ; ; - RIC selections ; 0000 0034 RIC_START equ $34 ; Start 8344 execution 0000 0030 RIC_DRAM equ $30 ; Select 8344 Data RAM 0000 0034 RIC_DRAM_RUN equ $34 ; Select 8344 Data RAM and do not stop 8344 0000 0031 RIC_IMEM equ $31 ; Select 8344 Instruction memory 0000 0032 RIC_PC_LO equ $32 ; Select 8344 Program Counter low byte 0000 0033 RIC_PC_HI equ $33 ; Select 8344 Program Counter high byte ; ; - BCP test states ; 0000 0000 bcpIDLE equ $00 ; BCP test not started 0000 0001 bcpRUNNING equ $01 ; BCP test in progress 0000 0002 bcpDONE equ $02 ; BCP test completed ; ; - BCP Tests entry points, low bytes ; 0000 0020 BT_POR equ $20 ; 8344 POR Test starts at 0020 ; ; - BCP test error bits ; 0000 0001 bcpRegErr equ $01 ; BCP register test failed 0000 0002 bcpLoopErr equ $02 ; BCP loop back test failed 0000 0010 bcpRamErr equ $10 ; BCP data RAM test failed 0000 0013 bcpError equ bcpRegErr + bcpLoopErr + bcpRamErr ; ; Misc. ; 0000 0800 BCP_IM_SIZE equ $800 ; size of bcp instruction memory (I.M.) 0000 1000 bcp_rdback equ $0001000 ; start location to store readback from 8344 I.M. 0002 0000 WaitBCPDone equ $00020000 ; loop count waiting for 8344 to finish testing 0000 5A6F VendID equ $5a6f ;unofficial Zorro Vendor ID MC68020 Assembler - Ver 2.88 14-Dec-88 Page 4 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement ;----------- sResource Directory stuff ; 0000 0001 sRsrc_Board EQU 1 ;Board sResource 0000 000A CommBoardId EQU $A ;Officially defined by Developer Technical Support 0000 0004 ROMRevLevel equ 4 ;ROM revision level (now D) must be < 9 0000 0080 sRsrc_CPU EQU 128 ;identify CPU & memory resources 0000 0081 sRsrc_Comm1 EQU 129 ;comm type 1 0000 0082 sRsrc_Comm2 EQU 130 ;comm type 2 0000 0083 sRsrc_Comm3 EQU 131 ;comm type 3 0000 0084 sRsrc_Comm4 EQU 132 ;comm type 4 0000 008C sRsrc_sMemory EQU 140 ;2nd leved sResource (not seen directly by slot manager) 0000 0096 CatsMemory EQU 150 ;not defined by DTS, 2nd level sRrsource 0000 0080 MinorRAMAddr EQU 128 0000 0082 MinorROMAddr EQU 130 0000 0084 MinorDeviceAddr EQU 132 0000 000A CatCPU EQU $000A ; 0000 0001 Typ68000 EQU $0001 ; 0000 FFFF DrSwNotThere EQU $FFFF ;Apple MCP has 68K, no on-board driver 0000 0001 DrHwAMCP EQU $0001 ;First generation Apple MCP cards 0000 0006 CatCommunication EQU $0006 ;mb CatInterface? 0000 0013 Typ3270 EQU $0013 ;vanilla 3270 for Zorro card 8/23/88 ;DrSwNotThere EQU $FFFF ;Apple MCP has 68K, no on-board driver ;DrHwAMCP EQU $0001 ;First generation Apple MCP cards ;CatCommunication EQU $0006 ;mb CatInterface? ;Typ3270 EQU $0013 ;vanilla 3270 for Zorro card 8/23/88 ;DrSwNotThere EQU $FFFF ;Apple MCP has 68K, no on-board driver 0000 0006 DrHwA3270_5250 EQU $0006 ;Apple 3270/5250 NB card (Zorro)-implies 8344 chip ;CatCommunication EQU $0006 ;mb CatInterface? 0000 000A Typ5250 EQU $000A ;5250 protocol (actual DTS constant is Typ32705250) ;DrSwNotThere EQU $FFFF ;Apple MCP has 68K, no on-board driver ;DrHwAMCP EQU $0001 ;First generation Apple MCP cards ;CatCommunication EQU $0006 ;mb CatInterface? ;Typ5250 EQU $000A ;5250 protocol (actual DTS constant is Typ32705250) ;DrSwNotThere EQU $FFFF ;Apple MCP has 68K, no on-board driver ;DrHwA3270_5250 EQU $0006 ;Apple 3270/5250 NB card (Zorro)-implies 8344 chip ;Include files PRINT ON 00000 CommROM MAIN 00000 STRING C 00000 00000 00000 ;=============================================================================== 00000 ; Power-On test 00000 ; The following jsr PowerOn must be the first instruction of code in the ROM. 00000 ; PowerOn tests RAM, ROM, & will then call the Vendor Powerup test defined in ApplPoweron.a 00000 ;=============================================================================== 00000 00000 IMPORT PowerOn ;from powerup.a 00000 00000 4EBA 0000 jsr PowerOn 00004 00004 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 00004 ; Resource Directory 00004 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 00004 ; 00004 _sRsrcDir OSLstEntry sRsrc_Board,_sRsrc_Board ; 00004 0100 001C 1 DC.L (sRsrc_Board<<24)+((_sRsrc_Board-*)**$00FFFFFF) ; MC68020 Assembler - Ver 2.88 14-Dec-88 Page 5 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement 00008 OSLstEntry sRsrc_CPU, _sRsrc_CPU ; defines CPU, MCP architecture 00008 8000 00A8 1 DC.L (sRsrc_CPU<<24)+((_sRsrc_CPU-*)**$00FFFFFF) ; 0000C OSLstEntry sRsrc_Comm1, _sRsrc_Comm1 ;category Communications 0000C 8100 0148 1 DC.L (sRsrc_Comm1<<24)+((_sRsrc_Comm1-*)**$00FFFFFF) ; 00010 OSLstEntry sRsrc_Comm2, _sRsrc_Comm2 ;category Communications 00010 8200 0180 1 DC.L (sRsrc_Comm2<<24)+((_sRsrc_Comm2-*)**$00FFFFFF) ; 00014 OSLstEntry sRsrc_Comm3, _sRsrc_Comm3 ;category Communications 00014 8300 01B4 1 DC.L (sRsrc_Comm3<<24)+((_sRsrc_Comm3-*)**$00FFFFFF) ; 00018 OSLstEntry sRsrc_Comm4, _sRsrc_Comm4 ;category Communications 00018 8400 01EC 1 DC.L (sRsrc_Comm4<<24)+((_sRsrc_Comm4-*)**$00FFFFFF) ; 0001C DatLstEntry EndOfList,0 ; <0> 0001C FF00 0000 1 DC.L (EndOfList<<24)+0 00020 00020 00020 00020 ;============================================================= 00020 ; sRsrc_Board List 00020 ;============================================================= 00020 ; 00020 _sRsrc_Board OSLstEntry sRsrc_Type,_BoardType ; 00020 0100 0018 1 DC.L (sRsrc_Type<<24)+((_BoardType-*)**$00FFFFFF) ; 00024 OSLstEntry sRsrc_Name,_BoardName ; 00024 0200 001C 1 DC.L (sRsrc_Name<<24)+((_BoardName-*)**$00FFFFFF) ; 00028 DatLstEntry BoardId,CommBoardId ; 00028 2000 000A 1 DC.L (BoardId<<24)+CommBoardId 0002C OSLstEntry PrimaryInit,_sPInitRec ; <_sPInitRec record offset> 0002C 2200 0210 1 DC.L (PrimaryInit<<24)+((_sPInitRec-*)**$00FFFFFF) ; 00030 OSLstEntry VendorInfo,_VendorInfo ; <_VendorInfo record offset> 00030 2400 0024 1 DC.L (VendorInfo<<24)+((_VendorInfo-*)**$00FFFFFF) ; 00034 DatLstEntry EndOfList,0 ; <0> 00034 FF00 0000 1 DC.L (EndOfList<<24)+0 00038 00038 0001 _BoardType DC.W CatBoard ;Board sResource : 0003A 0000 DC.W TypBoard ; 0003C 0000 DC.W 0 ; 0003E 0000 DC.W 0 ; 00040 4170706C652033 _BoardName DC.L 'Apple 3270/5250 NB' ;Official Name of Board 00054 00054 ;------------------------------------------------------------- 00054 ; Vendor Info record 00054 ;------------------------------------------------------------- 00054 _VendorInfo OSLstEntry VendorId,_VendorId ; 00054 0100 0010 1 DC.L (VendorId<<24)+((_VendorId-*)**$00FFFFFF) ; 00058 OSLstEntry RevLevel,_RevLevel ; 00058 0300 0030 1 DC.L (RevLevel<<24)+((_RevLevel-*)**$00FFFFFF) ; 0005C OSLstEntry PartNum,_PartNum ; 0005C 0400 0038 1 DC.L (PartNum<<24)+((_PartNum-*)**$00FFFFFF) ; 00060 DatLstEntry EndOfList,0 ; <0> 00060 FF00 0000 1 DC.L (EndOfList<<24)+0 00064 00064 436F7079726967 _VendorId DC.L 'Copyright (C) 1988 Apple Computer' ;Vendor Id 00088 524F4D20726576 _RevLevel DC.L 'ROM rev. D' ;Revision Level 00094 3334322D303632 _PartNum DC.L '342-0627 (H) 342-0626 (L)' ;Part Number 000B0 000B0 000B0 ;============================================================= 000B0 ; sRsrc_CPU List 000B0 ;============================================================= 000B0 ; 000B0 _sRsrc_CPU OSLstEntry sRsrc_Type,_CPUType ; 000B0 0100 0018 1 DC.L (sRsrc_Type<<24)+((_CPUType-*)**$00FFFFFF) ; 000B4 OSLstEntry sRsrc_Name,_CPUName ; 000B4 0200 001C 1 DC.L (sRsrc_Name<<24)+((_CPUName-*)**$00FFFFFF) ; 000B8 ; OSLstEntry sRsrc_DrvrDir,_ComDrvrDir ; 000BC OSLstEntry MinorLength, _MinorLength 000BC 0B00 0030 1 DC.L (MinorLength<<24)+((_MinorLength-*)**$00FFFFFF) ; 000C0 OSLstEntry sRsrc_sMemory, _sRsrc_sMemory ; defines card memory mapping 000C0 8C00 0030 1 DC.L (sRsrc_sMemory<<24)+((_sRsrc_sMemory-*)**$00FFFFFF) ; 000C4 DatLstEntry EndOfList,0 ; <0> 000C4 FF00 0000 1 DC.L (EndOfList<<24)+0 000C8 000C8 000A _CPUType DC.W CatCPU ;Board sResource : 000CA 0001 DC.W Typ68000 ; MC68020 Assembler - Ver 2.88 14-Dec-88 Page 6 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement 000CC FFFF DC.W DrSwNotThere ; 000CE 0001 DC.W DrHwAMCP ; 000D0 4350555F363830 _CPUName DC.L 'CPU_68000_none_AppleMCP' ;Name of CPU 000E8 000E8 0000 0000 _MinorBase DC.L 0 ;Offset is 0 000EC 0100 0000 _MinorLength DC.L $1000000 ;memory map length is 16 Meg 000F0 000F0 ;============================================================= 000F0 ; _sRsrc_sMemory List 000F0 ;============================================================= 000F0 ; 000F0 _sRsrc_sMemory OSLstEntry sRsrc_Type,_sMemoryType ; 000F0 0100 0018 1 DC.L (sRsrc_Type<<24)+((_sMemoryType-*)**$00FFFFFF) ; 000F4 OSLstEntry sRsrc_Name,_sMemoryName ; 000F4 0200 001C 1 DC.L (sRsrc_Name<<24)+((_sMemoryName-*)**$00FFFFFF) ; 000F8 OSLstEntry MinorRAMAddr, _MinorRAMAddr 000F8 8000 0020 1 DC.L (MinorRAMAddr<<24)+((_MinorRAMAddr-*)**$00FFFFFF) ; 000FC OSLstEntry MinorROMAddr, _MinorROMAddr 000FC 8200 0028 1 DC.L (MinorROMAddr<<24)+((_MinorROMAddr-*)**$00FFFFFF) ; 00100 OSLstEntry MinorDeviceAddr, _MinorDeviceAddr 00100 8400 0030 1 DC.L (MinorDeviceAddr<<24)+((_MinorDeviceAddr-*)**$00FFFFFF) ; 00104 DatLstEntry EndOfList,0 ; <0> 00104 FF00 0000 1 DC.L (EndOfList<<24)+0 00108 00108 0096 _sMemoryType DC.W CatsMemory ;Board sResource : 0010A 0001 DC.W 1 ; MCP type 0010C FFFF DC.W DrSwNotThere ; 0010E 0001 DC.W DrHwAMCP ; 00110 734D656D6F7279 _sMemoryName DC.L 'sMemory' ;Name of resource 00118 00118 0000 000C _MinorRAMAddr DC.L 12 ;block size in bytes 0011C 0040 0000 DC.L $400000 ;RAM length (Architecture allows up to 4 Meg) 00120 0000 0000 DC.L $0 ;RAM base offset 00124 00124 0000 000C _MinorROMAddr DC.L 12 ;block size in bytes 00128 0001 0000 DC.L $10000 ;ROM length (Architecture allows 64K) 0012C 00FF 0000 DC.L $FF0000 ;ROM base offset 00130 00130 0000 0024 _MinorDeviceAddr DC.L _EndMinorDeviceAddr - _MinorDeviceAddr ; Block size 00134 0040 0000 DC.L $400000 ;no decode/DTACK I/O interface logic length 00138 0040 0000 DC.L $400000 ;no decode/DTACK I/O interface logic offset 0013C 0020 0000 DC.L $200000 ;decode/DTACK I/O interface logic length 00140 0080 0000 DC.L $800000 ;decode/DTACK I/O interface logic offset 00144 0020 0000 DC.L $200000 ;NuBus control range length 00148 00A0 0000 DC.L $A00000 ;NuBus control range offset 0014C 0000 000B DC.L $00000b ;MCP control range length 00150 00C0 0000 DC.L $C00000 ;MCP control range offset 00154 0000 0154 _EndMinorDeviceAddr EQU * ; End of block 00154 00154 ;------------------------------------------------------------- 00154 ; Driver directory (not used) 00154 ;------------------------------------------------------------- 00154 ;_ComDrvrDir OSLstEntry sMacOS68020,_sMacOS68020 ; 00154 ; DatLstEntry EndOfList,0 ; <0> 00154 00154 00154 ;Driver-1 (68020). 00154 ;_sMacOS68020 DC.L _End020Drvr-_sMacOS68020 ;Physical Block Size 00154 ; INCLUDE 'ComDrvr.a' ;The Header/Code 00154 ;_End020Drvr EQU * 00154 STRING C 00154 00154 00154 ;============================================================= 00154 ; sRsrc_Comm1 List 00154 ;============================================================= 00154 ; 00154 _sRsrc_Comm1 OSLstEntry sRsrc_Type,_CommunicationType1 ; 00154 0100 0010 1 DC.L (sRsrc_Type<<24)+((_CommunicationType1-*)**$00FFFFFF) ; 00158 OSLstEntry sRsrc_Name,_CommunicationName1 ; 00158 0200 0014 1 DC.L (sRsrc_Name<<24)+((_CommunicationName1-*)**$00FFFFFF) ; 0015C DatLstEntry sRsrc_HWDevId,1 ;hardware device ID 0015C 0800 0001 1 DC.L (sRsrc_HWDevId<<24)+1 00160 DatLstEntry EndOfList,0 ; <0> 00160 FF00 0000 1 DC.L (EndOfList<<24)+0 MC68020 Assembler - Ver 2.88 14-Dec-88 Page 7 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement 00164 00164 0006 _CommunicationType1 DC.W CatCommunication ;Board sResource : 00166 0013 DC.W Typ3270 ; 00168 FFFF DC.W DrSwNotThere ; 0016A 0001 DC.W DrHwAMCP ; 0016C 436F6D6D756E69 _CommunicationName1 DC.L 'Communication_3270_none_AppleMCP' ;Name of resource 00190 ;============================================================= 00190 ; sRsrc_Comm2 List 00190 ;============================================================= 00190 ; 00190 _sRsrc_Comm2 OSLstEntry sRsrc_Type,_CommunicationType2 ; 00190 0100 0010 1 DC.L (sRsrc_Type<<24)+((_CommunicationType2-*)**$00FFFFFF) ; 00194 OSLstEntry sRsrc_Name,_CommunicationName2 ; 00194 0200 0014 1 DC.L (sRsrc_Name<<24)+((_CommunicationName2-*)**$00FFFFFF) ; 00198 DatLstEntry sRsrc_HWDevId,2 ;hardware device ID 00198 0800 0002 1 DC.L (sRsrc_HWDevId<<24)+2 0019C DatLstEntry EndOfList,0 ; <0> 0019C FF00 0000 1 DC.L (EndOfList<<24)+0 001A0 001A0 0006 _CommunicationType2 DC.W CatCommunication ;Board sResource : 001A2 0013 DC.W Typ3270 ; 001A4 FFFF DC.W DrSwNotThere ; 001A6 0006 DC.W DrHwA3270_5250 ;, implies 8344 chip 001A8 436F6D6D756E69 _CommunicationName2 DC.L 'Communication_3270_none_8344' ;Name of resource 001C8 ;============================================================= 001C8 ; sRsrc_Comm3 List 001C8 ;============================================================= 001C8 ; 001C8 _sRsrc_Comm3 OSLstEntry sRsrc_Type,_CommunicationType3 ; 001C8 0100 0010 1 DC.L (sRsrc_Type<<24)+((_CommunicationType3-*)**$00FFFFFF) ; 001CC OSLstEntry sRsrc_Name,_CommunicationName3 ; 001CC 0200 0014 1 DC.L (sRsrc_Name<<24)+((_CommunicationName3-*)**$00FFFFFF) ; 001D0 DatLstEntry sRsrc_HWDevId,3 ;hardware device ID 001D0 0800 0003 1 DC.L (sRsrc_HWDevId<<24)+3 001D4 DatLstEntry EndOfList,0 ; <0> 001D4 FF00 0000 1 DC.L (EndOfList<<24)+0 001D8 001D8 0006 _CommunicationType3 DC.W CatCommunication ;Board sResource : 001DA 000A DC.W Typ5250 ; 001DC FFFF DC.W DrSwNotThere ; 001DE 0001 DC.W DrHwAMCP ; 001E0 436F6D6D756E69 _CommunicationName3 DC.L 'Communication_5250_none_AppleMCP' ;Name of resource 00204 00204 ;============================================================= 00204 ; sRsrc_Comm4 List 00204 ;============================================================= 00204 ; 00204 _sRsrc_Comm4 OSLstEntry sRsrc_Type,_CommunicationType4 ; 00204 0100 0010 1 DC.L (sRsrc_Type<<24)+((_CommunicationType4-*)**$00FFFFFF) ; 00208 OSLstEntry sRsrc_Name,_CommunicationName4 ; 00208 0200 0014 1 DC.L (sRsrc_Name<<24)+((_CommunicationName4-*)**$00FFFFFF) ; 0020C DatLstEntry sRsrc_HWDevId,4 ;hardware device ID 0020C 0800 0004 1 DC.L (sRsrc_HWDevId<<24)+4 00210 DatLstEntry EndOfList,0 ; <0> 00210 FF00 0000 1 DC.L (EndOfList<<24)+0 00214 00214 0006 _CommunicationType4 DC.W CatCommunication ;Board sResource : 00216 000A DC.W Typ5250 ; 5250 00218 FFFF DC.W DrSwNotThere ; 0021A 0006 DC.W DrHwA3270_5250 ;, implies 8344 chip 0021C 436F6D6D756E69 _CommunicationName4 DC.L 'Communication_5250_none_8344' ;Name of resource 0023C 0023C 0023C ; DO NOT ADD ANYTHING BELOW THIS LINE OR THE PRIMARY INIT CODE WILL FAIL!!! 0023C 0023C 0023C ;------------------------------------------------------------- 0023C ; Primary Init Record 0023C ;------------------------------------------------------------- 0023C 0000 03BE _sPInitRec DC.L _EndsPInitRec-_sPInitRec ;Physical Block Size 00240 INCLUDE 'PrimaryInit.a' ;The Primary Init Header/Code 00240 ;****************************************************************************** 00240 ; 00240 ; File: CommInit.a 00240 ; Author: Michael Klassen, June 8, 1987 MC68020 Assembler - Ver 2.88 14-Dec-88 Page 8 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement 00240 ; Description: This file contains the MCP initialization code. 00240 ;------------------------------------------------------------------------------ 00240 ; Mod History: 00240 ; July 7, 1987 MK: Changed from 24 to 32 bit addressing mode 00240 ; 2 April 88 WHJW: Added code to safely change a 68K interrupt vect from 020 side 00240 ; 3 May 1988 WHJW: Added selftest LED indicator status for 3270 card vers. 00240 ; 30 June 88 MK: Added 2 second max timeout routine for powerup code wait 00240 ; 20 Sept 88 MK: Saved off registers & sr before executing primary init 00240 ; 12 Dec 1988 WHJW: L2 interrupt tested before tests requiring it are run 00240 ; Replaced NuBus W/R w/ 32 bit sliding 5's test 00240 ; 14 Dec 1988 WHJW: moved LED indicator status dependency to ApplPrimaryInit.a 00240 ; 00240 ;****************************************************************************** 00240 00240 ;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 00240 ; 00240 ; VERY IMPORTANT NOTE!!! DUE TO THE NATURE OF THE PRIMARY INIT CODE, IT MUST 00240 ; IMMEDIATELY PRECEED THE FORMAT HEADER BLOCK AT THE END OF THE ROM. DO NOT 00240 ; MOVE IT FROM THIS LOCATION! 00240 ;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 00240 00240 ;============================================================================== 00240 ; Header 00240 ;============================================================================== 00240 00240 02 dc.b sExec_2 ; code revision 00241 02 dc.b sCPU_68020 ; CPU type 00242 0000 dc.w 0 ; reserved 00244 0000 0004 dc.l Begin-* ; offset to code 00248 00248 ;============================================================================== 00248 ; Procedure 00248 ; On entry: A0 points to slot manager parameter block 00248 ; On exit: D0 contains board status (0 = OK) 00248 ;============================================================================== 00248 00248 WITH seBlock 00248 00248 ; Set initial vendor status and save vars. 00248 00248 48E7 FFFE Begin movem.l A0-A6/D0-D7,-(SP) 0024C 317C 0001 0002 MOVE.W #1,seStatus(A0) ;VendorStatus <- 1 {Code was executed} 00252 P 40E7 move.w SR,-(SP) ; push status register on stack 00254 2F08 MOVE.L A0,-(A7) ;save param block ptr 00256 00256 00256 ; Turn the slot number into a base address. 00256 00256 7000 MOVEQ #0,D0 ;D0 <- 00000000 00258 1010 MOVE.B seSlot(A0),D0 ;D0 <- 0000000s 0025A E148 LSL.W #8,D0 ;D0 <- 00000s00 0025C G 0040 F000 OR.W #$F000,D0 ;D0 <- 0000Fs00 00260 4840 SWAP D0 ;D0 <- Fs000000 00262 2440 MOVEA.L D0,A2 ;A2 <- Base address to the slot. 00264 00264 P 007C 0700 ori.w #$700,SR ; disable Mac Motherboard interrupts 00268 _m32 ; set 32-bit addressing 00268 2F00 1 move.l d0, -(a7) 0026A G 7001 1 move.l #1, d0 0026C A05D 1 _SwapMMUMode 0026E 201F 1 move.l (a7)+, d0 00270 00270 4EBA 02BA 0052C jsr OnRedGreen ;turn on red & green LED, if any WHJW:14 Dec 88 00274 00274 ; Wait for finish of power-on test. If timeout, return current error status 00274 00274 223C 0000 07D0 move.l #2000,D1 ; 2000 milliseconds max wait before timeout 0027A G 7401 waitlup move.l #1,D2 0027C 4EBA 00E8 00366 jsr waitCycles 00280 302A 0100 move.w WaitFlag(A2),D0 ; get WaitFlag 00284 0C40 0000 cmpi.w #OFF,D0 00288 6704 0028E beq.s waitEnd ; jif test done 0028A G 51C9 FFEE 0027A dbra D1,waitlup 0028E G 7000 waitEnd move.l #0,D0 00290 302A 0102 move.w TstStatus(A2),D0 ; get current status MC68020 Assembler - Ver 2.88 14-Dec-88 Page 9 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement 00294 G 0C41 0000 cmp #0,D1 ; did we timeout? 00298 6604 0029E bne.s chkStat ; jif no 0029A 4EFA 00A0 0033C jmp errExit 0029E 0029E ; Power-on test complete. Check status of test status register 0029E 0029E 2200 chkStat move.l D0,D1 002A0 0281 0000 001F andi.l #PowerMask,D1 ; turn off bits for later tests 002A6 0C81 0000 0000 cmpi.l #0,D1 ; have all power-on tests succeeded? 002AC 6704 002B2 beq.s BusTest ; jif so 002AE 4EFA 008C 0033C jmp errExit ; else return error flag 002B2 002B2 002B2 ; Nubus write/read test WHJW: made into sliding 5's test 7 Dec 88 002B2 002B2 7405 BusTest moveq #5, D2 ; slide a 5 thru card RAM addr 002B4 224A movea.l A2,A1 002B6 D2FC 0112 adda.l #WriteLoc,A1 ; point to RAM location (currently card loc $112) 002BA 2282 @again move.l D2, (A1) ; test all 32 data lines 002BC B491 cmp.l (A1), D2 002BE 6600 007C 0033C bne errExit ; failure, set status 002C2 E39A rol.l #1, D2 002C4 64F4 002BA bcc.s @again 002C6 0280 FFFF FFDF andi.l #BusMask,D0 002CC 3540 0102 move.w D0,TstStatus(A2) ; clear test bit flag 002D0 002D0 ;BusTest movea.l A2,A1 002D0 ; adda.l #WriteLoc,A1 ; point to write location 002D0 ; move.w #$F8A5,D2 002D0 ; move.w D2,(A1) ; write test value 002D0 ; move.w (A1),D3 ; read it back 002D0 ; cmp D2,D3 002D0 ; beq.s HITest 002D0 ; jmp errExit 002D0 ;HITest andi.l #BusMask,D0 002D0 ; move.w D0,TstStatus(A2) ; clear test bit flag 002D0 002D0 ; IOP interrupt test WHJW: moved ahead of card reset, timer interrupt tests 002D0 002D0 4EBA 0146 00418 jsr testIOP ; perform IOP level 2 interrupt test 002D4 0C81 0000 0000 cmpi.l #PASS,D1 002DA 6704 002E0 beq.s IOPTest ; jif so 002DC 4EFA 005E 0033C jmp errExit 002E0 0280 FFFF FEFF IOPTest andi.l #IOPMask,D0 ; clear test bit from status flag 002E6 3540 0102 move.w D0,TstStatus(A2) 002EA 002EA ; Reset card from Mac test 002EA 002EA 4EBA 00EC 003D8 jsr testHost ; perform host test 002EE 0C81 0000 0000 cmpi.l #PASS,D1 002F4 6704 002FA beq.s hostTest ; jif so 002F6 4EFA 0044 0033C jmp errExit 002FA 0280 FFFF FFBF hostTest andi.l #HostMask,D0 ; clear test bit from status flag 00300 3540 0102 move.w D0,TstStatus(A2) 00304 00304 ; Timer test 00304 00304 00304 4EBA 007C 00382 jsr Timer ; test card timer (level 1) interrupt 00308 0C81 0000 0000 cmpi.l #PASS,D1 0030E 6704 00314 beq.s timTest ; jif so 00310 4EFA 002A 0033C jmp errExit 00314 0280 FFFF FF7F timTest andi.l #TimeMask,D0 ; clear test bit from status flag 0031A 3540 0102 move.w D0,TstStatus(A2) 0031E 0031E ; Vendor specific test(s) 0031E 0031E 4EBA 0128 00448 jsr VendorPI ; do the vendor-supplied primary init test(s) 00322 0C81 0000 0000 cmpi.l #PASS,D1 00328 6704 0032E beq.s vendTest ; jif so 0032A 4EFA 0010 0033C jmp errExit 0032E 0280 FFFF FDFF vendTest andi.l #VendMask,D0 ; clear test bit from status flag 00334 3540 0102 move.w D0,TstStatus(A2) 00338 00338 ; Tests done, time to exit MC68020 Assembler - Ver 2.88 14-Dec-88 Page 10 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement 00338 00338 303C 0001 move.w #1,D0 ; status = good 0033C 0033C ; set the reset flag 0033C 0033C G 72FF errExit move.l #ON,D1 0033E 3541 0108 move.w D1,ResetFlag(A2) 00342 ; If &ROM='Zorro' Then ;WHJW: Set red or green LED for fail or pass 00342 ; move.l #$600001, d1 ;currently defined Zorro LED control register 00342 ; move.b #$2, (a2, d1.l) ;write to LED control register (turn on red only) 00342 4EBA 020C 00550 jsr OnRed ;assume the worst WHJW 14 Dec 88 00346 4A40 tst.w D0 ;passed all tests if D0 positive 00348 6B00 0006 00350 bmi @123 ;failed, leave on red LED 0034C 4EBA 01F0 0053E jsr OnGreen ;leave passed status: WHJW 14 Dec 88 00350 ; move.b #$1, (a2, d1.l) ;write to LED control register (turn on green only) 00350 ; Endif 00350 00350 @123 _m24 ; set 24-bit addressing 00350 2F00 1 move.l d0, -(a7) 00352 G 7000 1 move.l #0, d0 00354 A05D 1 _SwapMMUMode 00356 201F 1 move.l (a7)+, d0 00358 G 265F move.l (A7)+,A3 ; restore parameter block ptr 0035A 3740 0002 move.w D0,seStatus(A3) ; store test results 0035E P 46DF move.w (SP)+,SR ; restore Mac motherboard interrupts 00360 4CDF 7FFF movem.l (SP)+,A0-A6/D0-D7 00364 4E75 rts ; that's all folks! 00366 00366 ;**************************************************************************** 00366 ; waitCycles: 00366 ; wait the number of dbra cycles needed to delay d2.w milliseconds 00366 ; In: D2 = # of milliseconds 00366 00366 waitCycles ;wait at least d2.w milliseconds 00366 5342 subq #1, d2 ;dbxx quirk� 00368 2F00 move.l d0, -(sp) 0036A 2F08 move.l a0, -(sp) 0036C 307C 0D00 movea.l #TimeDBRA, a0 00370 3010 move.w (a0), d0 ;(TimeDBRA) contains # DBRAs/millisec 00372 G 51C8 FFFE 00372 @1 dbra d0, @1 00376 3010 move.w (a0), d0 00378 G 51CA FFF8 00372 dbra d2, @1 ;wait at least d2.w msec 0037C G 205F move.l (sp)+, a0 0037E 201F move.l (sp)+, d0 00380 4E75 rts 00382 00382 ;***************************************************************************** 00382 ; Timer: Test the card's timer interrupt 00382 ; In: D0 = current test status, do not clobber. A2 = slot Addr 00382 ; Out: D1 = PASS or FAIL 00382 00382 357C FFFF 0104 Timer move.w #FAIL,TimeFlag(A2) ; Failure if timeout 00388 282A 0064 move.l $64(A2),D4 ; save old timer interrupt vector 0038C 2A2A 0068 move.l $68(A2),D5 ; save old level 2 interrupt vector 00390 243C 00FF FF80 move.l #TimeAddr,D2 00396 2542 0148 move.l D2, L1IntAddr(A2) ; move new interrupt into low mem 0039A 257C 00FF FF60 move.l #SetL1Addr, $68(a2) ; 68000 must set L1 interrupt 0068 003A2 G 284A move.l A2,A4 003A4 D9FC 00C0 000A adda.l #SetIOPIntr,A4 ; this L2 interrupt sets L1 interrupt 003AA G 3854 move.w (A4),A4 ; trigger timer interrupt set routine 003AC G 7410 move.l #TimerWait,D2 003AE 4EBA FFB6 00366 jsr waitCycles ; wait for timer interrupt to occur 003B2 322A 0104 move.w TimeFlag(A2),D1 ; save timer test status in d1 003B6 003B6 2544 0148 move.l D4, L1IntAddr(A2) ; move old interrupt into low mem 003BA 257C 00FF FF60 move.l #SetL1Addr, $68(a2) ; 68000 must set L1 interrupt 0068 003C2 G 284A move.l A2,A4 003C4 D9FC 00C0 000A adda.l #SetIOPIntr,A4 ; sets L1 interrupt 003CA G 3854 move.w (A4),A4 ; trigger timer interrupt set routine 003CC G 7410 move.l #TimerWait,D2 003CE 4EBA FF96 00366 jsr waitCycles ; wait for timer interrupt to occur 003D2 2545 0068 move.l D5,$68(A2) ; restore old level 2 interupt vector 003D6 4E75 rts MC68020 Assembler - Ver 2.88 14-Dec-88 Page 11 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement 003D8 003D8 003D8 ;****************************************************************************** 003D8 ; testHost: 003D8 ; Test the ability of the host to reset the 68000 003D8 ; In: D0 = current test status, do not clobber. A2 = slot base addr 003D8 ; Out: D1 = PASS or FAIL 003D8 003D8 282A 0004 testHost move.l 4(A2),D4 ; save old interrupt vector 003DC 243C 00FF FFA0 move.l #HostAddr,D2 ; put address of interrupt rtn 003E2 2542 0004 move.l D2,4(A2) ; into reset vector slot 003E6 357C FFFF 0106 move.w #FAIL,HostFlag(A2) ; set the hostflag 003EC 263C 00F0 0000 move.l #Reset,D3 ; reset the 68000 003F2 224A movea.l A2,A1 003F4 D3C3 adda.l D3,A1 003F6 3283 move.w D3,(A1) ; write does the reset 003F8 G 7404 move.l #Delay,D2 003FA 4EBA FF6A 00366 jsr waitCycles ; give 68000 time to process interrupt 003FE 224A movea.l A2,A1 00400 D3FC 00C0 0000 adda.l #ExtReg,A1 00406 3611 move.w (A1),D3 ; clear reset and trigger test routine 00408 G 7404 move.l #TimeCnt,D2 0040A 4EBA FF5A 00366 jsr waitCycles ; wait for test routine on 68000 0040E 322A 0106 move.w HostFlag(A2),D1 ; get test result 00412 2544 0004 move.l D4,4(A2) 00416 4E75 rts 00418 00418 00418 ;**************************************************************************** 00418 ; testIOP: 00418 ; Test the ability of the Mac Motherboard to interrupt the card's 68000. 00418 ; In: D0 = current test status, do not clobber. A2 = slot base addr 00418 ; Out: D1 = PASS or FAIL 00418 00418 282A 0068 testIOP move.l $68(A2),D4 ; save old interrupt vector 0041C 243C 00FF FFC0 move.l #IOPAddr,D2 00422 2542 0068 move.l D2,$68(A2) ; put addr of test routine into vector 00426 357C FFFF 010C move.w #FAIL,IOPFlag(A2) ; set the IOPflag 0042C 263C 00C0 000A move.l #SetIOPIntr,D3 ; interrupt the 68000 00432 G 224A move.l A2,A1 00434 D3C3 adda.l D3,A1 00436 3611 move.w (A1),D3 ; read does the interrupt 00438 G 7404 move.l #TimeCnt,D2 0043A 4EBA FF2A 00366 jsr waitCycles ; give 68000 time to process interrupt 0043E 322A 010C move.w IOPFlag(A2),D1 ; get test result 00442 2544 0068 move.l D4,$68(A2) ; restore interrupt vector 00446 4E75 rts 00448 00448 ;***************************************************************************** 00448 ; VendorPI: Execute the vendor supplied test of the card 00448 ; In: D0 = current test status, do not clobber. A2 = slot Addr 00448 ; A3 = ptr to Slot Manager parameter block 00448 ; Out: D1 = PASS or FAIL 00448 00448 INCLUDE 'ApplPrimaryInit.a' 00448 00448 ;=================================================================================== 00448 ; 00448 ; File: ApplPrimaryInit.a 00448 ; 00448 ; Entry: VendorPI 00448 ; 00448 ; Function: Zorro initialization code 00448 ; { 00448 ; for (count = loopcount; ((count >0) && (bcpTestState != DONE)); count--) {}; 00448 ; if ((bcpTestState != DONE) || (bcpTestErr)) 00448 ; error(); 00448 ; stop_bcp(); 00448 ; Test 8344 Data RAM locations 0x0000-0x3FFF with patterns FF, AA, 55, and 00; 00448 ; Test 8344 address lines; 00448 ; } 00448 ; 00448 ; Input: D0 = Current current test state 00448 ; A2 = slot address 00448 ; A3 = ptr to Slot Manager parameter block MC68020 Assembler - Ver 2.88 14-Dec-88 Page 12 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement 00448 ; 00448 ; Output: D1 = PASS or FAIL 00448 ; ($138) = 32 bit failure code if D1 == FAIL 00448 ; 00448 ; Update: D0, A2, A3 preserved 00448 ; 00448 ; History: 12/03/87: initial version 00448 ; 00448 ;=================================================================================== 00448 MC68020 Assembler - Ver 2.88 14-Dec-88 Page 13 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement 00448 ;bcpRIC equ $420001 ; 8344 remote interface configuration register 00448 ;bcpPC equ $400001 ; Dummy address for writing to 8344 PC 00448 ;bcpDRAM equ $400001 ; 8344 Data RAM address base 00448 ;bcpDMEnd equ $4000 * 2 + bcpDRAM ; Last data memory + 1 00448 ;RIC_DRAM equ $30 ; Select 8344 Data RAM 00448 ;PASS equ 0 00448 ;FAIL equ -1 00448 00448 VendorPI: 00448 2F00 move.l D0, -(sp) ; save test state 0044A 2F0A move.l A2, -(sp) ; save slot address 0044C 2F0B move.l A3, -(sp) ; save Slot Mgr Parameter block ptr 0044E 2540 0150 move.l D0, $150(A2) 00452 2541 0154 move.l D1, $154(A2) 00456 2542 0158 move.l D2, $158(A2) 0045A 2543 015C move.l D3, $15C(A2) 0045E 2548 0160 move.l A0, $160(A2) 00462 2549 0164 move.l A1, $164(A2) 00466 254A 0168 move.l A2, $168(A2) 0046A 254B 016C move.l A3, $16C(A2) 0046E 0046E ; 0046E ; - Test 8344 Data RAM 0046E ; 0046E 0046E 287C 0040 0001 movea.l #bcpDRAM, A4 ; point to location 0000 of data memory 00474 D9CA adda.l A2, A4 ; add slot address 00476 267C 0040 8001 movea.l #bcpDMEnd, A3 ; ending location 0047C D7CA adda.l A2, A3 ; add slot address 0047E 4EBA 0052 004D2 jsr zi_RAM ; test interface area (0x0000 - 0x3FFF) 00482 6604 00488 bne.s zi_err ; skip if error 00484 G 7200 move.l #PASS, D1 ; no error 00486 6002 0048A bra.s zi_rtn ; exit 00488 00488 ;--------------------------------------- 00488 ; - Error exit 00488 ;--------------------------------------- 00488 00488 zi_err: 00488 G 72FF move.l #FAIL, D1 ; test failed 0048A 0048A ;--------------------------------------- 0048A ; - Exit 0048A ;--------------------------------------- 0048A 0048A zi_rtn: 0048A 2540 0170 move.l D0, $170(A2) 0048E 2541 0174 move.l D1, $174(A2) 00492 2542 0178 move.l D2, $178(A2) 00496 2543 017C move.l D3, $17C(A2) 0049A 2548 0180 move.l A0, $180(A2) 0049E 2549 0184 move.l A1, $184(A2) 004A2 254A 0188 move.l A2, $188(A2) 004A6 254B 018C move.l A3, $18C(A2) 004AA G 265F move.l (sp)+, A3 ; restore Slot Mgr Parameter block ptr 004AC G 245F move.l (sp)+, A2 ; restore slot address 004AE 201F move.l (sp)+, D0 ; restore test state 004B0 2540 0190 move.l D0, $190(A2) 004B4 2541 0194 move.l D1, $194(A2) 004B8 2542 0198 move.l D2, $198(A2) 004BC 2543 019C move.l D3, $19C(A2) 004C0 2548 01A0 move.l A0, $1A0(A2) 004C4 2549 01A4 move.l A1, $1A4(A2) 004C8 254A 01A8 move.l A2, $1A8(A2) 004CC 254B 01AC move.l A3, $1AC(A2) 004D0 004D0 4E75 rts 004D2 MC68020 Assembler - Ver 2.88 14-Dec-88 Page 14 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement 004D2 004D2 ;=================================================================================== 004D2 ; 004D2 ; Name: zi_RAM 004D2 ; 004D2 ; Function: Test 8344 Data Memory 004D2 ; 004D2 ; Input: A4 = starting RAM address 004D2 ; A3 = ending RAM address + 1 004D2 ; A2 = slot address 004D2 ; 004D2 ; Output: Z flag set => no error 004D2 ; Z flag clear => error (D1 = data written; D2 = data read back; 004D2 ; A4 = failed address) 004D2 ; 004D2 ; Update: None 004D2 ; 004D2 ; History: 12/03/87: initial version 004D2 ; 004D2 ;=================================================================================== 004D2 004D2 zi_RAM: 004D2 227C 0042 0001 movea.l #bcpRIC, A1 ; address of 8344 RIC 004D8 D3CA adda.l A2, A1 ; NuBus address 004DA 260C move.l A4, D3 ; save starting location 004DC 7030 moveq #RIC_DRAM, D0 ; select Data memory 004DE 1280 move.b D0, (A1) ; 004E0 123C 00FF move.b #$FF,D1 ; data pattern 004E4 @1: 004E4 1881 move.b D1, (A4) ; write to memory 004E6 B214 cmp.b (A4), D1 ; read it back check 004E8 663A 00524 bne.s @90 ; jump if errror 004EA 004EA 548C addq.l #2, A4 ; addr.ptr++ 004EC G B9CB cmp.l A3, A4 ; check if reached end 004EE 66F4 004E4 bne.s @1 004F0 004F0 2843 movea.l D3, A4 ; reset pointer to where it started 004F2 7255 moveq #$55,D1 ; data pattern 004F4 @2: 004F4 1881 move.b D1, (A4) ; write to memory 004F6 B214 cmp.b (A4), D1 ; read it back check 004F8 662A 00524 bne.s @90 ; jump if errror 004FA 004FA 548C addq.l #2, A4 ; addr.ptr++ 004FC G B9CB cmp.l A3, A4 ; check if reached end 004FE 66F4 004F4 bne.s @2 00500 00500 2843 movea.l D3, A4 ; reset pointer to where it started 00502 123C 00AA move.b #$AA,D1 ; data pattern 00506 @3: 00506 1881 move.b D1, (A4) ; write to memory 00508 B214 cmp.b (A4), D1 ; read it back check 0050A 6618 00524 bne.s @90 ; jump if errror 0050C 0050C 548C addq.l #2, A4 ; addr.ptr++ 0050E G B9CB cmp.l A3, A4 ; check if reached end 00510 66F4 00506 bne.s @3 00512 00512 2843 movea.l D3, A4 ; reset pointer to where it started 00514 7200 moveq #$00,D1 ; data pattern 00516 @4: 00516 1881 move.b D1, (A4) ; write to memory 00518 B214 cmp.b (A4), D1 ; read it back check 0051A 6608 00524 bne.s @90 ; jump if errror 0051C 0051C 548C addq.l #2, A4 ; addr.ptr++ 0051E G B9CB cmp.l A3, A4 ; check if reached end 00520 66F4 00516 bne.s @4 00522 00522 4E75 rts ; good return 00524 @90: 00524 1414 move.b (A4), D2 ; D2 = data read back 00526 163C 0001 move.b #1, D3 ; insure Z = 0 0052A 4E75 rts ; return MC68020 Assembler - Ver 2.88 14-Dec-88 Page 15 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement 0052C 0052C 0052C ;=================================================================================== 0052C ; Entry: (Status indicator routines) 0052C ; 0052C ; Function: 0052C ; When execution of primary init begins, both OnRed & OnGreen are 0052C ; called, indicating that the test is in progress. if primary init crashes 0052C ; it will then be evident that the test did not complete. If any tests fail, 0052C ; the routine OffGreen is called to leave on the red LED, and if all self-tests 0052C ; pass, the routine OffRed is called. 0052C ; 0052C ; If your card uses some other mechanism to indicate good (green) or bad (red) 0052C ; status, feel free to change the function (but not the name) of these routines. 0052C ; 0052C ; Remember that the following routines are executed across NuBus, and therefore 0052C ; 32 bit NuBus addressing must be used. 0052C ;=================================================================================== 0052C 0052C OnRedGreen: ;turn on red & green LED or do whatever to indicate test running 0052C ;Reg A2 contains the 32 bit base address of the card 0052C 2F01 move.l d1, -(sp) ;save & restore any registers changed 0052E 223C 0060 0001 move.l #$600001, d1 ;currently defined Zorro LED control register 00534 15BC 0003 1800 move.b #$3, (a2, d1.l) ;write to LED control register (turn on red only) 0053A 221F move.l (sp)+, d1 0053C 4E75 rts 0053E 0053E OnGreen: ;turn on green LED or do whatever to indicate good status 0053E ;Reg A2 contains the 32 bit base address of the card 0053E 2F01 move.l d1, -(sp) ;save & restore any registers changed 00540 223C 0060 0001 move.l #$600001, d1 ;currently defined Zorro LED control register 00546 15BC 0001 1800 move.b #$1, (a2, d1.l) ;write to LED control register (turn on green only) 0054C 221F move.l (sp)+, d1 0054E 4E75 rts 00550 00550 OnRed: ;turn on red LED 00550 ;Reg A2 contains the 32 bit base address of the card 00550 2F01 move.l d1, -(sp) ;save & restore any registers changed 00552 223C 0060 0001 move.l #$600001, d1 ;currently defined Zorro LED control register 00558 15BC 0002 1800 move.b #$2, (a2, d1.l) ;write to LED control register (turn on red only) 0055E 221F move.l (sp)+, d1 00560 4E75 rts 00562 00562 OffRedGreen: ;turn off green LED 00562 ;Reg A2 contains the 32 bit base address of the card 00562 2F01 move.l d1, -(sp) ;save & restore any registers changed 00564 223C 0060 0001 move.l #$600001, d1 ;currently defined Zorro LED control register 0056A G 4232 1800 move.b #$0, (a2, d1.l) ;write to LED control register (turn off green only) 0056E 221F move.l (sp)+, d1 00570 4E75 rts 00572 MC68020 Assembler - Ver 2.88 14-Dec-88 Page 16 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement 00572 00572 ;**************************************************************************** 00572 ; 68000 interrupt tests. 00572 ; Note: due to the nature of the init code, these must be the very last 00572 ; things in the declaration ROM before the format header block. 00572 ; DO NOT MOVE OR THE PRIMARY INIT CODE WILL NOT WORK!!!!! 00572 00572 ;The following level 2 interrupt allows the host processor to change the level 1 interrupt. 00572 ; If the host processor did this directly, there is a real chance an interrupt vector 00572 ; read could get a word of the old and a word of the new interrupt vector & crash� 00572 00572 SetL1Interrupt ;This line must be at ROM location $FFFF60 00572 2F08 move.l a0, -(sp) ; level 1 interrupts are disabled on a L 2 interrupt 00574 207C 00C0 0008 movea.l #ClrIOPIntr,a0 0057A G 3050 move.w (a0),a0 ; clear this level 2 interrupt 0057C G 91C8 moveq.l #0, a0 0057E 2168 0148 0064 move.l L1IntAddr(a0), $64(a0) ;location where Mac processor put L1 intrupt vect. 00584 G 205F move.l (sp)+, a0 00586 P 4E73 rte 00588 4E71 nop ;padding for further development 0058A 4E71 nop 0058C 4E71 nop 0058E 4E71 nop 00590 4E71 nop 00592 00592 TimeInt 00592 2F09 move.l A1,-(SP) 00594 2F00 move.l D0,-(SP) 00596 227C 00C0 0002 movea.l #TimerSet, A1 0059C 3011 move.w (A1), D0 ; clear timer interrupt 0059E 327C 0104 movea.l #TimeFlag,A1 005A2 G 4251 move.w #PASS,(A1) ; If get here, its a PASS 005A4 327C 0118 movea.l #timeCountAddr, A1 005A8 5291 addq.l #1, (A1) ; incr timer location 005AA 201F move.l (SP)+,D0 005AC G 225F move.l (SP)+,A1 005AE P 4E73 rte 005B0 4E71 nop 005B2 005B2 2F08 HostInt move.l A0,-(SP) 005B4 307C 0106 movea.l #HostFlag,A0 005B8 G 4250 move.w #PASS,(A0) ; If get here, its a PASS 005BA G 205F move.l (SP)+,A0 005BC P 027C F8FF andi.w #$F8FF,SR ; enable all interrupts 005C0 4E72 2000 Host1 stop #$2000 005C4 4EFA FFFA 005C0 jmp Host1 005C8 4E71 nop ; padding for further development 005CA 4E71 nop 005CC 4E71 nop 005CE 4E71 nop 005D0 4E71 nop 005D2 005D2 2F08 IOPInt move.l A0,-(SP) 005D4 2F09 move.l A1,-(SP) 005D6 227C 00C0 0008 movea.l #ClrIOPIntr,A1 ; clear the interrupt 005DC 3211 move.w (A1),D1 005DE 307C 010C movea.l #IOPFlag,A0 005E2 G 4250 move.w #PASS,(A0) ; If get here, its a PASS 005E4 G 225F move.l (SP)+,A1 005E6 G 205F move.l (SP)+,A0 005E8 P 4E73 rte 005EA 4E71 nop ; padding for further development 005EC 4E71 nop 005EE 4E71 nop 005F0 4E71 nop 005F2 4E71 nop 005F4 4E71 nop 005F6 4E71 nop 005F8 4E71 nop 005FA 0000 05FA _EndsPInitRec EQU * ;End of block 005FA STRING C 005FA 005FA 5A6F DC.W VendID ; unofficial 3270/5250 id 005FC C3D2 DC.W CommID ; unofficial MCP architecture id 005FE ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ MC68020 Assembler - Ver 2.88 14-Dec-88 Page 17 Copyright Apple Computer, Inc. 1984-1987 Loc F Object Code Addr M Source Statement 005FE ; Format/Header Block 005FE ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 005FE 00FF FA06 DC.L (_sRsrcDir-*)**$00FFFFFF ;Offset to sResource directory 00602 0001 0000 DC.L ROMSize ;Length of declaration data 00606 0000 0000 DC.L 0 ;CRC {Patched by crcPatch} 0060A 04 DC.B ROMRevLevel ;ROM Revision level defined in application.h 0060B 01 DC.B AppleFormat ;Format 0060C 5A93 2BC7 DC.L TestPattern ;Test pattern 00610 00 DC.B 0 ;Reserved byte 00611 0F DC.B $0F ;ByteLanes: 0000 1111 00612 00612 ENDP END Elapsed time: 11.03 seconds. Assembly complete - no errors found. 1578 lines.