SWIM III Data Register 50F16000 Read or write to or from FIFO. Selected by DMAack input regardless of values on address bus Timer Register 50F16200 A 1us timer register. Values loaded into this register will decrement at a 1us rate. The first count after the load can occur at any time byt all subsequent counts will be 1u apart. For example a load of 2 will timeout in >1us but <2us. The count rate is independent of the setting of the clock divide bit. An interrupt is generated when the count equals zero. Error Register 50F16400 Indicates the type of error that has occured. Cleared on a reset or on read. Only one error can be set at a time. Must be cleared prior to a read or write. If any of these bits are set the error flag in the Handshake register will be set. Errors on reads only function in MFM mode and after the mark byte is found. Data 0 Underrun FIFO. FIFO empty while writing or full and not read during a read. Data 1 Not Used. (Was mark byte read from data register) Data 2 Overrun FIFO. FIFO written while full in write mode or read while empty in read mode. Data 3 not used Data 4 not used Data 5 not used Data 6 CRC error on address mark Data 7 CRC error on data field Parameter Data 50F16600 The parameter ram has be reduced to two nibbles of data, early time and late time. The data is stored as {late time, early time}. The nominal, no precomp value is $7. Phase Register 50F16800 Data bits 0-3 represent phase line 0-3. Data bits 4-7 are not used. Setup Register 50F16A00 This register sets the various modes of operation. It is reset to all zeros except as noted. Data 0 =0 don't invert wrdata (neg pulses) =1 invert wrdata (pos pulses) Data 1 =1 copy protection mode Causes a change in operation to support copy protection. When set, all data from the next mark byte will be transfered, not stopping until the go bit is set false. The transfered data will consis to two bytes per byte of read data. The first byte is $00 unless it was a mark byte in which case a $80 is transfered. The second byte is the data. Data 2 =0 MFM mode; =1 GCR Mode Data 3 =0 normal; =1 clock divided by two. Note the clock to SWIM2 may be different than SWIM. If supplied a 16M clock SWIM2 will read and write 2,3,4 us MFM cells and 2,4,6 us GCR cells with this bit set to zero. With a 32M clock input SWIM2 will read and write 1,1.5,2 us MFM cells, and should have this bit set to one to generate 2,3,4 us MFM cells and 2,4,6 us GCR cells. Data 4 Disable GCR conversion. If set to one disable the conversion tables in GCR mode for copy protection Data 5 0=Apple data mode; 1=IBM mode. (0=NRZ data, 1=RZ data.) Data 6 =0 MFM writes; =1 GCR data writes. Data 7 Mode/Status Register 50F16C00 Mode/Handshake Register 50F16E00 Data 0 Mark Next byte in FIFO = Mark byte. Data 1 =0 Data 2 RDData Direct read of drive data Data 3 Sense Direct read of rdddata input Data 4 =0 was motor still on Data 5 Error A bit in the error register is set Data 6 Dat2bytes FIFO empty in write or full in read when 1 Data 7 Dat1byte FIFO has at least one byte in it. This signal is gated with error in write mode so that if a write error occurs the SWIM will appear empty so to not cause the software to hang. Mode register Zeros @ C00 Ones @ E00 The mode register is controlled bit by bit by writing either the write zeros or write ones location with the bits that are being modified set to one. To make bit 0 a zero write 00000001 to location C00, to make it a one write 00000001 to location E00. Reset sets all bits to zero. Data 0 Enable interrupts 1 = enabled Data 1 Enable 1 1 = enable drive 1 Data 2 Enable 2 1 = enable drive 2 Data 3 Go 1 = Go active (was action) Data 4 Write 1 = write mode; 0 = read. Data 5 Side Sel 1 = side 1; 0 = side 0 Data 6 Format mode (new) Data 7 Go_step 1 = Start stepping to desired track Interrupt Register 50F17000 Cleared by read Data 0 1=Timer count =0 Data 1 Step Done 1=Stepping complete Data 2 ID read 1 = just read address header Data 3 Sectors_done 1= just finished reading last byte of a sector (read mode) or just got the end_data command(write mode) or process terminate by error Data 4 Sense change 1 = (sense line just changed) Useful for generating an interrupt when a disk is inserted or when waiting for ready/ to signal the drive is ready. Step Register 50F17200 Load this register with the number of steps needed to be moved after the direction is set in the drive and step address is placed on the phase lines. This register is automatically decremented by the hardware after each step command is sent to the drive and an interrupt (step_done) is generatoed when the last step is taken. No step commands are sent until the go_step bit is set. An 80us timeout is made between every step. The step_done interrupt is set under this condition as well. Current Track Register 50F17400 The 7 LSB's of this register holds the last track ID read from the drive. Bit 8 of this register is the last head ID read from the drive. Resets to $ff. Current Sector Register 50F17600 The 7 LSB's of this register holds the last sector ID read from the drive. This value may be stale as indicated by the Last_ID_valid bit. Bit 8 of this register hold the Last_ID_valid bit. This bit is set after reading a sector id when either the crc is correct or the checksum is ok (gcr). It is cleared during the data field header or when go is turned off. The register resets to $7f. Gap/Format Register 50F17800 This register should be loaded with the number of "pad" bytes to be transfered after the data bytes in a multiple sector read operation. When read back it contains the format byte. First_Sector Register 50F17A00 The first 6 bits of this register should be loaded with the first sector number desired to be read or written. The transfers will start when this sector is found. If bit 6 is set to a one (x1xxxxxx) any sector will match and be transfered. Resets to $ff. Sectors_To_Xfer Register 50F17C00 This register is loaded with the number of sectors desired to be accessed continuously. After each sector the hardware will decrement this value until it reaches zero. The number of untransfered sectors will be retained here after an error has occured. Resets to $00. Interrupt Mask Register 50F17E00 Masks interrupts in register $8 bit for bit. Setting a one enables each bit, a zero disables a bit. ----- SWIM II ======= 50F16000 Data Register Read or write data to or from FIFO 50F16200 Mark Register Read or write Mark bytes 50F16400 Error/Write CRC Register On Reads indicates type of error that occured. Cleared on a reset or on a read. Only one error can be set at a time. Must be cleared prior to a read or write. If any of these bits are set the error flag in the Handshake register will be set. Errors on reads only function in MFM mode after the mark byte is found. Bit 0 Underrun FIFO Fifo empty while writing or full and not read during read. Bit 1 Mark in Data Mark byte read from data register Bit 2 Overrun FIFO FIFO wrtten while full in write mode or read while empty in read mode. Bit 3 Not used (was correction error) Bit 4 Transition too short Bit 5 Transition too long Bit 6 Not used (was unresolved transition) Bit 7 Not used (not used on SWIM) On writes, sets the CRC bit in the fifo, causing the CRC to be written after the last bit of the data. 50F16600 Parameter Data Register Sets addresses of parameter RAM Address Data 00 Late/xxxx (first nibble only) 01 Time0 (defines step increment, hardwired) (set to 1us in MFM, 2us in GCR) (based on 16m clock) 10 Early/xxxx (first nibble only) 11 Time1 (not used) 50F16800 Phase Register The phase lines can be programmed as either inputs or outputs. Data bits 0-3 represent phases lines 0-3. Data bits 4-7 act as data direction control bits for the phase lines 0-3, with a 1 meaning output. 50F16A00 Setup Register This register sets the various modes of operation. It is reset to all zeros except as noted. Bit 0 Invert wrdata 0=dont invert (neg pulses) 1=invert (pos pulses) (was able to select Q3 as output) Bit 1 2.5 general purpose output Bit 2 MFM/GCR mode 0=MFM mode 1=GCR mode Bit 3 clock divider 0=normal 1=clock divided by 2 Bit 4 Test mode causes bytes of zeros to appear at phase register. Bit 5 IBM/Apple data mode 0=Apple data mode 1=IBM data mode Bit 6 Write data mode 0=MFM writes 1=GCR writes Bit 7 (was motor timeout) Always 0 50F16C00 Mode Register Bit 0 Clear FIFO 1 = clear fifo Bit 1 Enable1 1 = enable drive 1 Bit 2 Enable2 1 = enable drive 2 Bit 3 Action 1 = Action set Bit 4 Write mode 1 = write 0 = read Bit 5 Side Select 1 = side 1 0 = side 0 Bit 6 not used always reads 1 Bit 7 Motor On 0 = motor disabled, 1 = enable drive 1 or 2 To clear bits in this register, write the appropriate pattern containing the bits to be cleared to 50F16C00. To set bits in this register, write the appropriate pattern containing the bits to be set to 50F16E00 50F16E00 Handshake register Bit 0 Mark Next byte in FIFO = Mark Bit 1 CRC zero CRC was zero, valid when 2nd CRC byte is about to be read from FIFO. Bit 2 RdData Direct read of drive data Bit 3 Sense Direct read of sense input Bit 4 not used Always zero Bit 5 Error A bit in the error register is set Bit 6 dat2bytes FiFO empty in write or full in read when = 1 Bit 7 Dat1byte FIFO has at least 1 byte in it