Bryan Parkoff wrote: > CLC > SED > LDA #\$20 > ADC #\$FA > CLD > EOR #\$80 > BMI +\$03 > STA 2000 > RTS Nothing is guaranteed if decimal mode is used to add non-BCD values. All nibbles need to be in the range 0..9, so \$FA is definitely invalid. You might find the attached fragment from a C=64 emulator document interesting. It was written by John West and Marko MŠkelŠ (and uses "than" a lot in place of "as" ;-): ================================================= Decimal mode in NMOS 6500 series Most sources claim that the NMOS 6500 series sets the N, V and Z flags unpredictably when performing addition or subtraction in decimal mode. Of course, this is not true. While testing how the flags are set, I also wanted to see what happens if you use illegal BCD values. ADC works in Decimal mode in a quite complicated way. It is amazing how it can do that all in a single cycle. Here's a C code version of the instruction: unsigned A, /* Accumulator */ AL, /* low nybble of accumulator */ AH, /* high nybble of accumulator */ C, /* Carry flag */ Z, /* Zero flag */ V, /* oVerflow flag */ N, /* Negative flag */ s; /* value to be added to Accumulator */ AL = (A & 15) + (s & 15) + C; /* Calculate the lower nybble. */ AH = (A >> 4) + (s >> 4) + (AL > 15); /* Calculate the upper nybble. */ if (AL > 9) AL += 6; /* BCD fixup for lower nybble. */ Z = ((A + s + C) & 255 != 0); /* Zero flag is set just like in Binary mode. */ /* Negative and Overflow flags are set with the same logic than in Binary mode, but after fixing the lower nybble. */ N = (AH & 8 != 0); V = ((AH << 4) ^ A) & 128 && !((A ^ s) & 128); if (AH > 9) AH += 6; /* BCD fixup for upper nybble. */ /* Carry is the only flag set after fixing the result. */ C = (AH > 15); A = ((AH << 4) | (AL & 15)) & 255; The C flag is set as the quiche eaters expect, but the N and V flags are set after fixing the lower nybble but before fixing the upper one. They use the same logic than binary mode ADC. The Z flag is set before any BCD fixup, so the D flag does not have any influence on it. Proof: The following test program tests all 131072 ADC combinations in Decimal mode, and aborts with BRK if anything breaks this theory. If everything goes well, it ends in RTS. begin 600 dadc M 0@9",D'GL(H-#,IJC(U-JS"*#0T*:HR-@ 'BI&* A/N\$_\$B@+)\$KH(V1 M*Q@(I?PI#X7]I?LI#V7]R0J0 FD%J"D/A?VE^RGP9?PI\ C \$) ":0^JL @H ML ?)H) &""@X:5\X!?V%_0AH*3W@ ! ""8"HBD7[\$ JE^T7\, 28"4"H**7[ M9?S0!)@) J@8N/BE^V7\V A%_= G:(3]1?W0(.;[T(?F_-"#:\$D8\ )88*D= 0&&4KA?NI &4LA?RI.&S[ A% end ============================================== -michael Check out amazing quality 8-bit Apple sound on my Home page: http://members.aol.com/MJMahon/