Mountain Hardware Clock Parallel Serial (CPS) card information These are some notes I exchanged with somebody about this card. Note that I no longer have the card or the manual, so I can no longer provide more information. But see the routines provided with Kermit-65 for more info about using this card. Adrian. -------------------------------------------- > Thanks for the reply and the offer. I believe that what I have is > the CPS card that you mentioned. It has a 1981 date silk screened > on the pcb. Yes, that's the one. > > I think that the serial port may be the easiest to use, because I > think that the UART is visible at addresses $CnF8-B. I haven't tested > this. I do have the kermit files, and can look at these. Thanks for the > suggestion. I have the data sheets for the 2651 UART. OK, here we go. From the Mountain Computer Incorporated (MCI) CPS Multifunction card Operating Manual, Appendix B Advanced programmers Information: General Organization. The card uses the I/O select addressing area of the Apple's peripheral slot space; the $C800 space is not used. the I/O select area uses the Cnxx addresses (where n is the slot number). No device select addresses (C08x + n0) are used, so the card cannot be used in slot 0. The 2K of ROM is mapped as eight banks, each bank occupying the same area, from Cn00 to CnEF. The area from CnF0 to CnF7 is occupied by 32 eight byte banks of non-volatile RAM and teh top eight addresses are used for device control and registers. Address location CNFE contains the following: (these descriptions go LSB D0 to MSB D7, unless otherwise noted) Clock address bits +CA0 through +CA3, clock read (+CR), clock write (+CW), clock hold (+CH) and the serial control register multiplexer bit (+SCR). The +SCR bit selects which set of serial control regiters (address CnFA through CnFB) are in use. Address location CnFD contains the following: Parallel data out byte (bit +PO7 is MSB) Address location CnFC contains the following: apple peripheral I/O slot map (+I/O 1 to 7), high bit indicates phantom slot allocation. Address location CnFB contains the following: PCI command register contents (+SCR = 1) Transmit enable (+TXEN), Data terminal redy (+DTR), Receive enable (+RXEN), Async force break (BRK) of Sync send DLE (DLE)*, reset error (+RE), request to send (+RTS), operating mode bit 0 (+OM0) and bit 1 (+OM1). PCI status mode register contents (+SCR bit = 0) Read 1 Transmit holding register ready (+TXRDY), receive holding register ready (+RXRDY), change in DSR or DCD or transmit shift register is empty (TXEMPT), assync. mode parity error (+PE) or sync mode parity error/DLE character received (DLE)*, overrun error (+OVRN), assync framing error (+FE) or sync SYN character detected*, data carrier detected (DCD), data set ready (DSR). Write 1 and Write 2 sync byte (SY0 - SY7)* write 3 DLE byte* PCI mode register-1 contents (+SCR = 1) Mode and baud rate factor (+BRF0 and +BRF1), character length (+CL0 and +CL1), parity control enabled (+PE), parity type even (+PT). * synchronous mode is not supported by MCI. Over the page is a neat memory map (called a "Hardware location summary"). The easiest thing to do would be for me to scan it in and send it to you as a GIF or JPEG, assuming you have some way of looking at such files. Otherwise, I could try typing in the information it contains. Simply, the info is CnFA: (SCR = 1) PCI mode register, described above. and (SCR = 0), serial data I/O register CnF9: D7: spare input TTL input line (eg could be used as a shift key detector). pinout is (pinout is the little J3 jumper block at upper left, closest the keyboard) J3-1 input, J3-2 ground. Initialized state: 1. D6: Parallel/Serial port +0BE Initialized state: 1. D5-D4: not used. D3-D0: clock data (D3 MSB). CnF8 D7-D4: RAM bank select (LSB's), D3: RAM bank select (MSB), D2-D0: ROM bank select CnF7 I/O select default (RAM bank 0 only). > > I have puzzled out part of the schematic and once built a clock card > with the same chip used on this board. The clock address lines and > data need to be latched because the chip is too slow, as you say. Was that the article "Time for the Apple"? > > Perhaps you could answer the following questions to help me along. > > 1) What is the function of the jumper with "C" and "D" next to it at > lower right of the card? When I first tried the card, my disk wouldn't > boot. Things ran only after I pulled the jumper plug. With the plug in, > the LS245 line driver seems to be clobbering the whole $Cnxx address > space and preventing the disk from being recognized. Surely, this was > not the intended effect of this jumper. "The CPS card supports the ability to mask out other cards and trap their calls. This allows the multiple devices on the card to be mapped to slots other than that in which the CPS card is actually located. "This is done by using the 'USER1' line on the Apple bus. We know of no other peripherals which use this line, but if you acquire one you will need to understand how that line is used. The DIP carrier at H-12 (on the Apple motherboard) gives the CPS card access to the USER1 line (AFTER the jumper on the motherboard), which inhibits ALL cards which use I/O SELECT to activate their chip enables. "Briefly, the USER1 line when low pulls both DEVICE SELECT and I/O SELECT high. The CPS card uses address decoding but NOT I/O SELECT as chip enables. Therefore, when the USER1 line is low the CPS card will not be disabled, but all other cards which use either DEVICE SELECT and I/O SELECT will be disabled. This is independent of the state of the USER1 JUMPER on the motherboard. The register at CnF7 is a mask which determines whether or not the selected slot will be disabled or not. "The only obvious way that thee can ever be contention is if another card is present which uses address coding for its chip enablesrather than the standard use of DEVICE SELECT and I/O SELECT. Under these circumstances (assuming that the CPS card byte at CnF7) has the bit for that slot set tru) it is possible for both cards to compete for the bus. "You must clear the appropriate bit of the byte at CnF7 to prevent trapping of the other slots calls, under these (admittedly unlikely) circumstances. If you ever have difficulty reaching a peripheral card, the first thing to try is the monitor command 'CnF0:0' (from BASIC: 'POKE -16137+n*256,0, where n must be the ACTUAL slot number), and then press RESET. This will transfer the default value to the runtime location and disable all phantom slots. If this doesn't help, then the problem probably does not originate on the CPS card." and elsewhere: "Be EXTREMELY careful if you use the 'phantom slot' mechanism directly. You could mask out your disk controller and be unable to reboot! If you get into this difficulty, see Chaper 4." which suggests two temporary solutions: a) if the CPS default output device is connected and ON, type: PR#n (n = CPS slot number) CTRL-W D PR#0 b) enter th following phantom slot deselect program: 10 D$=CHR$(4):W$=CHR$(23) 20 PRINT D$;"PR#n":REM n=CPS slot # 30 PRINT W$;"D" 40 PRINT D$;"PR#0" 50 END and two permanent SOLUTIONS a) move the device to an unassigned slot b) perform the following: 1. press RESET 2. boot the CPS diskette 3. run the setup programm and select the slot assignments menu 4. enter the slot number of the conflicting device 5. enter "N" and leave the setup program. When using Pascal, I've used the following if some catastrophe has left the CPS card in a strange state: 1. power down Apple 2. disconnect batteries from CPS card 3. power up 4. reconnect batteries (yeah, I know, not good, but the card has survived so far (touching wood as I type!) 5. reset date in clock In Chapter 1 Installation, the following is found: "If your disk drive will not boot, one of three things is probably wrong: 1. the 2 pin cable is plugged in backwards (from J6 on the CPS card to the 74LS138 at H-12 on the Apple motherboard) 2. The CPS card is trying to use your disk slot as a phantom slot (detailed above) 3. a dead battery (how old are they???) or invalid RAM I/O select parameters are disabling some or all Apple peripheral slots. Use the solution (from the monitor) detailed above. also: "Note: CPS cards at Revision F and above (marked on the lower left component side of the card) contain an I/O select jumper. This jumper, when removed, will enable all Apple peripheral slots. If you cannot access a peripheral device (disk drive etc.), remove the jumper and try again." > > 2) What addresses does the clock use? I have the data sheet for the > clock chip and there seems to be a control and a data address. Where > are they? CnFE D6: clock hold, D5: clock write, D4: clock read, D3-D0: Clock address bits (D3 MSB) CnF9 D3-D0: Clock data (D3 MSB) > > 3) Does the documentation include a schematic? If it does, I would > dearly love to send you a self addressed envelope and the cost of > copying to get a copy. Schematics were often included back in those > earlier hacker days. Unfortunately there is no schematic (complete circuit diagram). There are pinouts for the various jumper block pins: J1-1 Ground J1-2 External transfer clock I/O J2-1 Ground J2-2 External receiver clock I/O J3-1 spare TTL input J3-2 ground Serial I/O: J4-1 chassis ground J4-2 TXD J4-3 RXD J4-4 RTS J4-5 CTS J4-6 DSR J4-7 signal ground J4-8 DCD J4-9 through J4-19 no connection J4-20 DTR J4-21 through J4-25 no connection J4-26 +12VDC Parallel I/O: J5-1 signal ground J5-2 ACK J5-3 through J5-7 no connection J5-8 STROBE (open collector) J5-9 no connection J5-10 DATA 0 J5-11 DATA 1 J5-12 DATA 2 J5-13 DATA 3 J5-14 DATA 4 J5-15 DATA 5 J5-16 DATA 6 J5-17 DATA 7 J5-18 no connection J5-19 no connection J5-20 signal ground Note: just to be difficult, the serial pin numbering order is different to the other blocks: top edge of card -------------------------------------------------------------------------- 1 1 1 14 26 19 3 1 . . . . . . . . . . . . . . . . . . . . . . . . . . J1 J2 J3 J4 J5 . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 2 1 13 20 4 2