That is the most information I've ever seen on the
mega II.  Does anyone have detailed documentation,
pinouts?

I'd like to know more about it's ram refresh circuitry,
and pinout so I can stick one on my own PCB.

It would need all connections from CPU, the
address and data lines could be in parallel with
RAM lines...  MMU must have some pins
to select which RAM chips to access.

Rich



quoted from
http://www.byte.com/art/9610/s=ADec4/art2.htm

""
The Mega II

The Mega II is a custom CMOS chip containing about 3000 gates and a
2K-byte by 8 ROM (for the character generator). It replaces the fol
lowing chips from the Apple IIe and IIc: character generator ROMs for
eight languages, several TTL chips that perform logic functions, and
the MMU (memory management unit), IOU (input/output unit), TMG (timing
generator), and GLU (general logic unit) custom chips.

In previous Apple II designs, the refreshing of memory was tied
directly to the Apple II video mode. The Mega II includes an 8-bit
counter for refreshing the 128K bytes of (slow) memory associated with
the Apple IIe/IIc model; it does five cycles of RAM refresh during the
horizontal retrace of each video scan line and refreshes the 128K bytes
of memory in 3.25 milliseconds. By taking care of RAM refresh, the Mega
II chip opens the Apple II design to new video modes that were
impossible before.=20
""