Ed Eastman <noone@nowhere.net> writes:
> 200ns chips can be acess 5 Million times a second or at up to 5 MHz.

That's true if the chip has a 200ns CYCLE TIME.  But a chip described
as 200 ns has a 200 ns ACCESS TIME.  The access time is the time from
when the address is strobed (for multiplexed-address DRAMs, the row
address) to when the data is valid.  The cycle time is generally much
longer than the access time.

> 2.8 MHz access time would require 357ns chips or faster (smaller
> number).  So a 400 ns chip (I've never seen one) would be at best,
> marginal.

If you make three simplifying assumptions:

1.  There are no delays due to buffering and multiplexing.

2.  The memory controller asserts RAS as early in the cycle
    as possible, based on the clock-to-address-valid spec of the
    65816.

3.  The timing specifications in the current data sheet for the
    W65C816S at 4.0 MHz apply to the part in the IIgs.  (I don't
    have the original data sheet from the mid-1980s handy.)  The
    4 MHz spec is at 2.5V, but is likely still better than the
    spec of the original part at 5.0V.

A 65C816 needs DRAM with an access time no longer than
tCyc (actual) - tADS (max) - tDSR (min).

The data sheet doesn'tt actually specify a minimum tDSR directly,
but it can be derived from tCyc (min) - tADS (max) - tACC (min),
which is  250 ns - 75 ns - 130 ns, or 45 ns.

So the 2.86 MHz 65C816 requires RAM access time no longer than
349 ns - 75 ns - 45 ns = 229 ns.  And the cycle time must be no
longer than 349 ns.

The assumptions, however, are not valid.

1.  The Apple IIgs does have additional delays due to buffers and
    multiplexers on the main logic board and on the memory expansion
    card.

2.  In the Apple IIgs, The RAS strobe is generated synchronously to the
    clock divider, and does not occur at the earliest possible time.

3.  The Apple IIgs uses an earlier version of the 65816 which probably
    has worse setup and hold time specifications than those of the
    current W65C816S (even the 4.0 MHz and 2.5V spec).

Therefore, DRAM for use on a memory expansion card for the IIgs should
have substantially better ratings than required by the simplified
analysis.

Apple used 100 ns access time DRAM on both the main logic board and
the memory expansion board.  In the absence of more detailed information
about the timing circuitry of the IIgs, I'd personally be reluctant
to use RAM with an access time specification longer than that.

Eric