This is a multi-part message in MIME format. --------------090103030301040405030809 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Peter Ibbotson wrote: > Michael is right. IIRC the problem is in the hold time on the data bus the > cmos part removes the data too quickly for the data bus latches to work > reliably. One of the Apple //e tech notes discusses the problem (In this > case between a 6502 and a 6502A but the same thing applies). There's a one-wire mod which lets most 'C02s work on a II+. I dug the attached up from Bob Sander-Cederlof's 'Assembly Lines' newsletter. It worked fine on my II+. --------------090103030301040405030809 Content-Type: text/plain; name="Another65C02Fix.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="Another65C02Fix.txt" A Different Patch for 65C02 & Old Apples...William O'Ryan Jr. Since my earlier letter (Jun 84) on the 65C02 and the Apple II+ I was interested and gratified to read Andrew Jackson's (Dec 84) and Jim Sather's (Mar 85) letters on the same subject. However, two things began to worry me. First, the smallness of the time gain in the F257 chips (around 7 nanoseconds, I understand). That did not seem enough to be very reliable. Second, a friend in town has an Apple whose speed was not sufficiently improved to allow the 65C02 to work (although there was some noticeable improvement). After reading the first few chapters of Jim Sather's book, "Understanding the Apple II", I was able to come up with a new solution. As I figure it, this new solution yields an improvement of around 70 nanoseconds, more than enough. Simply put, just replace the -RAS line inputs to the 74LS174 chips at B5 and B8 with AX. AX rises 70 nsec earlier than -RAS, enabling those chips to latch RAM output 70 nsec earlier. It is a simple patch and may be done either with or without altering the motherboard. I tried it first without altering my motherboard, on a Rev 44-1 Apple using 200 nsec 16K RAM chips. I was surprised to see it work, as I had expected that 200 nsec RAM chips would be too slow for the patch. (I haven't tried it yet with 250 nsec RAM chips.) Actually, this particular Apple did not need any speed-up -- the 65C02 was already working in it. To do this patch: remove the chips at B5 and B8; seat an extra socket under each of them; pin 9 on these sockets should be bent out so they do not go into the motherboard sockets; remove the chip at C2 and put an extra socket under it; connect a wire from pin 14 of the C2 socket to the bent out pins 9 of B5 and B8. Pin 14 of the 74S195 at C2 is a source of the AX signal; pin 9 of B5 and B8 was previously connected to -RAS. <<>> I have another Apple (Rev 4) which has 24 150 nsec 64K RAM chips (using the Cramapple mod). This Apple already had F257's in it with a 65C02. I put the old LS257's back in, and sure enough the 65C02 began to stumble. Then I removed the motherboard and on the underside cut the trace to -RAS and soldered in a jumper wire to pin 14 of C2. It worked perfectly! <<>> Naturally those who try any of these patches do so at their own risk. I must thank Jim Sather for his book; it was only by studying the timing diagrams in that book and staring at the circuit diagram published by Apple that I was able to do this. I hope some of the hardware types will be able to tell me if I have built a time bomb. I am also very interested to hear whether the problem with the 65802 is the same. Jumper wires Pins 9 not plugged into RAS View from top front 74LS195 74LS174 74LS174 AX Underside of motherboard viewed from rear Jumper wire Cut trace here AX RAS RAM --------------090103030301040405030809-- In <8GednYCGI7qaVomiXTWJiQ@comcast.com> Bill Garber wrote: > I have yet to find a 65C02 that works, I've tried NCR and GTE and I > think the only Rockwell I have is in a good working IIc and I'll not > jeopardize that to update a II+. Bob Sander-Cederlof's Apple Assembly Lines, available at Scott Alfter's web site , has an article on putting a 65C02 in an Apple II+. This is from the December 1984 issue: More Detail on Using 65C02's in old Apples......Andrew Jackson In recent issues of AAL there have been several articles on the 65C02 and how to get it running in the Apple II+. I too was keen to get a 65C02 working in my machine, and had spent some time trying to get first a 1MHz part and then a 2MHz part to work. William D. O'Ryan's letter in the June 84 AAL prompted me to try again and I am happy to report that the modification he described does work ( replacing the LS257's at B6 and B7 with F257's). I wanted to find exactly why I could not simply substitute a 65C02 for a 6502, and so I spent some time looking at the circuit and specifications, using an oscilloscope to check my results. The reasons that I eventually came up with are as follows. The Apple II circuit relies on various 'features' of the 6502 so that all the various parts of the Apple will work. The circuit diagram shows that the system timing is derived from o/0; the 6502 actually expects system timing to be derived from o/2. There is a slight delay between these two signals: on a 6502 it is about 50ns and on a 65C02 it is about 30ns. This difference in delays is what causes the problems when fitting a 65C02. To simplify its circuit design the Apple uses a rather dirty trick when reading data from RAM memory. Normally when the 6502 reads data it expects the data on the bus to be valid 100ns before the end of o/2, and it latches the data into its internal registers when o/2 changes. The setup time allows the data bus to settle into a consistent state before being read. The Apple reduces the setup time to about 45 ns ( worst case). This setup time would be ample for the 65C02 were it not for the shift between o/0 and o/2; this shift reduces the setup time to 25ns. A 2MHz 65C02 specifies a MINIMUM 40ns setup time; obviously there is a -15ns tolerance on the setup time, and hence the processor works erratically when timings fall into worst case conditions. The tolerance is regained by substituting 74F257's for the two 74LS257's at board locations B6 and B7. These two chips multiplex the RAM data and the keyboard data; in doing so they add a delay of 30ns worst case to the data. By substituting F257's, the added delay is reduced to 5 ns; this changes the tolerance on the data setup time from -15ns to +10ns. The Apple //e must use a slightly modified technique when reading data from RAM which explains why a 65C02 works in it without any modifications. I cannot check this as I do not have a //e circuit description. Anyway, it is probably all inside the MMU chip. [ The 65816 specifications state a minimum read data setup time of 50ns, 10ns longer than the 65C02. One AAL reader has called us to report that the 65802 works wonderfully well in his old II+, even better than the original 6502. Some of you have wondered where to get the F257's: try Jameco Electronics, 1355 Shoreway Road, Belmont, CA 94002, phone (415) 592-8097. Their ad in Byte, Dec '84, page 349, says they have 74F257's at $1.79 each. (editor) ] -- Roger Johnstone, Invercargill, New Zealand Apple II - FutureCop:LAPD - iMac Game Wizard http://homepages.ihug.co.nz/~rojaws/ ________________________________________________________________________ No Silicon Heaven? Preposterous! Where would all the calculators go? Kryten, from the Red Dwarf episode "The Last Day"