Roy and/or Janet Miller wrote: > Supertimer wrote: > > > Mainly the fact that the IIe treats the memory as an 8-bit > > computer would and the IIGS treats its memory as a > > 16-bit computer with a 24-bit address would. The IIe can > > only see 64k of memory at once, > > Actually, the 6502 and 65816, like all CPUs with an 8 bit data bus, only see > one byte at at time. Pedant. :-) > > 1MB on a IIe is really 16 banks of 64k. 1MB on a IIGS > > is 1MB. > > 1 MB on the 65816 is 16 banks of 64K, just like on an 8088. The IIgs may be nominally regarded as addressing 1 MB as 16 banks of 64 KB, but it has instructions that can directly access any of these locations without requiring bank switching. The address space can be treated as a single linear chunk as far as data is concerned. The division of memory into 64K banks is only significant in the following areas: - Execution of code cannot cross 64K boundaries without doing a far jump, call, return or interrupt. There is an 8-bit program bank register which keeps track of the active bank for executing code. - "Bank 0" (the first 64K) has special properties, namely it is the only place where the "direct page" and stack can be located, contains the interrupt vectors, and is the only bank which can be used safely for code execution in emulation mode. Indexing modes which offset from the direct page register or stack pointer will wrap around within bank 0. - There is a data bank register, which identifies the 64K bank being used for addressing modes that would normally reference a 16-bit address, e.g. "absolute" (and its indexed derivatives), and "direct page indirect". Any indexed variant of these modes can cross the 64K boundary and index into the following page. The IIgs imposes further bank restrictions, due to its memory organisation (and the legacy of emulating an 8-bit Apple II). The DMA hardware has an 8-bit DMA bank register, so a single DMA transfer sequence cannot cross a 64KB boundary. Banks 0, 1, $E0 and $E1 have the same memory structure as an 8-bit Apple II, i.e. 48KB of RAM at $0000-$BFFF, then I/O space at $C000-$CFFF and a language card from $D000-$FFFF (with two 4KB banks at $D000), or ROM in the same location. Banks $E0 and $E1 are implemented by the "Mega II" chip and are the physical (but not logical) equivalents of main and auxiliary memory for an Apple IIe or IIc. They contain the video buffers, and run at 1 MHz. Banks 0 and 1 are the logical equivalents of main and auxiliary memory for the Apple IIe or IIc. They contain shadowed versions of the video buffers (writes are duplicted into the real video buffers in banks $E0 and $E1), and can run at "fast" speed (2.6 MHz). Banks 2 through $7F are "fast RAM", with no special bank usage rules. Applications must use the Memory Manager to allocate memory in this area, but can potentially treat the whole lot as a single 7.875 MB linearly addressed area (assuming nothing else needs to allocate any memory, and you have 8MB of RAM installed). Banks $F0 and higher are ROM, or reserved for ROM expansion or a third party ROM disk. These don't have any specific bank associated restrictions. Banks $80 through $DF and $E2 through $EF are not implemented in the hardware. Another issue is that the processor only has 16 bit index registers, so it is not possible to access a data structure larger than 64 KB unless the base pointer variable is modified (or a temporary modified copy is used). Indexing may cross physical bank boundaries, so there is no general requirement that a 64 KB data structure be aligned with a bank address. e.g. you could have a 64KB data buffer starting at $02B01F, and ending at $03B01E. > The 6502 can only address a single bank of 64K. To address more, different > banks (or pages from different banks) have to be switched in and out of > that address space, just like EMS on an IBM would do. The 65816 can > address 256 banks of 64K. Except they are only nominally "banks" and are not bank-switched. > The 8086/8 can address 16 banks of 64K. Not exactly. It can address 1 MB, but uses a segmented architecture which only allows access to up to four 64 KB segments at a time. The segments can be aligned on any 16 byte boundary within the 1 MB address space. (These 16 byte blocks are referred to as "paragraphs".) The segments (code, data, stack and extra) may overlap, coincide or be completely separate. If you want to address a data structure larger than 64 KB, you have to change the contents of a segment register (usually the extra segment register). The IBM PC has one further hardware restriction related to physical 64 KB boundaries: the DMA hardware is implemented as an 8-bit bank register with 16-bit offset, and a single DMA transfer cannot cross a physical 64 KB boundary. This complicates the code in the floppy disk driver, since it has to do two transfers when crossing such a boundary. (I think this is normally handled by using a buffer in low memory, and software copying the data to the appropriate location.) Now, who is being pedantic? :-) -- David Empson dempson@actrix.gen.nz Snail mail: P O Box 27-103, Wellington, New Zealand