Anthony Khoury <akhouryr@ulb.ac.be> wrote:

> I'm looking for detailed information about the APPLE2C processor.

I assume you mean IIc+ (as in the subject line).

> Can someone send me info (Block diagram...) or advices some good
> websites ?

The details are in the second edition of the Apple IIc Technical
Reference.  It used to be available as a looseleaf photocopied manual
from Byte Works, but I forget who has taken over distribution of the
APDA products.  My copy is buried a little too deeply to grab hold of
right now.

In short, the IIc+'s CPU is the equivalent of a 4 MHz ZipChip
accelerator, but it is separated out into multiple components rather
than being bonded into a single package.

My recollection is that the major components are the 65C02 CPU (4 MHz),
ZipChip ASIC, and two 8 KB static RAM chips (for tag and data memory).

The ASIC is responsible for managing the cache, controlling the CPU
speed, and synchronizing with the rest of the motherboard.

As far as main memory and other components are concerned, the CPU is
just a standard 65C02 running at 1.027 MHz, as normal.  The CPU can
operate at full speed (4 MHz) when reading data which is already
available in the cache (as long as a normal memory location is being
accessed - I/O locations in the $Cxxx area are not cached).

For write operations, or for read operations which are not cached, the
ASIC synchronizes with the main system clock and the CPU then does a
normal access cycle (with the data being saved in the cache if
appropriate).

The ASIC also provides various timed delay mechanisms which allow
time-critical I/O operations like 5.25" disk accesses to work correctly
while the accelerator is enabled.

The firmware has some support routines for controlling the accelerator
without having to tweak the hardware directly, but as far as I know, the
hardware implementation is identical to a ZipChip.

-- 
David Empson
dempson@actrix.gen.nz