Newsgroups: comp.sys.apple2.comm Subject: Re: Accelerator Cards for 2E/2GS From: dempson@actrix.gen.nz (David Empson) Date: Tue, 24 Nov 1998 02:11:26 +1300 Message-ID: <1diz63a.1q5uy3k1eh5i2sN@dempson.actrix.gen.nz> References: <365053dc.5299832@news.mindspring.com> <1dint6w.1yfp7vt1ifpjbuN@dempson.actrix.gen.nz> <3658152f.7807930@news.mindspring.com> Organization: Empsoft X-Newsreader: MacSOUP 2.3 NNTP-Posting-Host: 202.49.157.176 X-Trace: 24 Nov 1998 02:09:38 -1300, 202.49.157.176 Lines: 107 Path: news1.icaen!news.uiowa.edu!NewsNG.Chicago.Qual.Net!nyd.news.ans.net!newsfeeds.ans.net!news.idt.net!newsfeed.cwix.com!203.97.37.7!newsfeed.clear.net.nz!news.iprolink.co.nz!news.actrix.gen.nz!dempson Xref: news1.icaen comp.sys.apple2.comm:5298 Vernon Bartlett wrote: > On Wed, 18 Nov 1998 22:47:08 +1300, in comp.sys.apple2.comm > dempson@actrix.gen.nz (David Empson) wrote: > > >You can't. Well, strictly speaking you can, but it is a very bad idea. > >The 65816 redefines several pins, including reversing the signal > >directions on some pins, and feeding a bank address out the data bus > >during the first half of each cycle (when the data bus is supposed to be > >idle for a 6502 or 65C02). > > Thanks for the comments Dave. You are a wealth of info. Ever worked > for Apple? Nope. Never even been to the USA. Almost everything I know about the Apple II is from personal experimentation and/or reading about it in Apple's vast collection of manuals (most of which I own). > I knew the 65815 and 65c02 were not pin for pin compatible but I > didn't know signals got reversed. Well, the pins in question are used for totally different functions on the 65C02 and 65816, and some of these happen to include a reversal of the signal direction. From a quick glance at the pinout, here are the major differences: 65C02/65802 65816 1 Ground Vector Pull (output) 3 Phase 1 clock (output) Abort (input) 5 No Connection Memory Lock (output) 7 Sync (output) Valid Program Address (output) 35 No Connection Emulation status (output) 36 No Connection Bus Enable (input) 38 Set Overflow (input) M/X status (output) 39 Phase 2 clock (output) Valid Data Address (output) (There is also the data bus, which has a bank address on it as mentioned earlier.) The most serious difference is pin 1: if this is tied to ground on the circuit board (as it is on the Apple II motherboard), then plugging in a 65816 will cause its vector pull output to be shorted to ground. This signal is normally high, so this isn't very good for it. Some of the control signals (abort and bus enable) would not be driven by the circuit board, which may cause them to float to an undefined state, increasing power consumption and possibly causing random aborts and bus floats. (This depends on whether the CPU has an internal pullup on these inputs.) The Sync output on the CPU (65C02) goes to all the slots, and can be used by cards to identify an opcode fetch (e.g. for a debugging card). This won't work any more if you replace the CPU with a 65816. The other signals are less of a problem on the Apple II motherboard, as the clock outputs of the CPU are not used, and neither is Set Overflow. On an accelerator, on the other hand, all bets are off. The card might be using the Sync output and clock signals for something important, and putting a 65816 on there would prevent it from operating. Trying to use native mode of the '816 may also cause problems, depending on how the accelerator interacts with the CPU (if it has any timing dependencies or watches instructions for doing some special operations). The bank address being on the data bus during the first half of the cycle is likely to cause continuous signal collisions, which will increase system noise, increase power consumption and reduce reliability. It could also prevent an accelerator from operating. > Do you remember if the 65802 ran at 4Mhz also? Yes. I don't recall a version faster than 4 MHz ever being made. > The reason I'm asking is if I did manage to find the chip and boost up > the timing, what other timing circuits would need to be compensated on > the 2e mother board if the crystal is replaced.. (I've got some old > scrap to play with here.) As David Wilson noted, you cannot increase the motherboard speed in the IIe (or any Apple II) without breaking everything. The video circuitry is intimately tied to the memory and CPU mechanisms, and all clock signals are derived from one master clock (14.31818 MHz in the US IIe). The IIgs gets around this by isolating the video circuitry to interact with RAM in a "slow" area of memory which is forced to run at 1 MHz, while the CPU is able to operate in "fast" mode when not using these memory areas. There is a special ASIC (the Fast Processor Interface) that ties the two halves of the system together, but it is also speed-dependent, so you can't change the "fast" side of the IIgs either. Accelerators work by using caching or memory imaging techniques to provide speed improvements. They watch for CPU accesses to areas of memory that must be performed in sync with the motherboard (video buffers and the I/O space), and run these cycles in sync at 1 MHz (or 2.8 MHz in the case of fast memory accesses on the IIgs). At other times, the accelerator can run at full speed using its own memory. Depending on DMA compatibility requirements, the accelerator may force write cycles to run in sync with the motherboard. If the card is not DMA compatible (as with all IIe accelerators) then it doesn't need to worry about this. -- David Empson dempson@actrix.gen.nz Snail mail: P.O. Box 27-103, Wellington, New Zealand