Project Information d:\progs\cffa\pldlogic\version2.0dev\appleideinterface.rpt MAX+plus II Compiler Report File Version 10.23 07/09/2003 Compiled: 02/16/2006 00:20:27 Copyright (C) 1988-2003 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein. ***** Project compilation was successful Title: Apple II IDE/CompactFlash Interface Company: R&D Automation Designer: Richard Dreher Rev: A Date: 10:34p 1-17-2006 ** DEVICE SUMMARY ** Chip/ Input Output Bidir Shareable POF Device Pins Pins Pins LCs Expanders % Utilized appleideinterface EPM7032STC44-10 16 16 0 20 0 62 % User Pins: 16 16 0 Project Information d:\progs\cffa\pldlogic\version2.0dev\appleideinterface.rpt ** AUTO GLOBAL SIGNALS ** INFO: Signal '7Mclk' chosen for auto global Clock Project Information d:\progs\cffa\pldlogic\version2.0dev\appleideinterface.rpt ** PIN/LOCATION/CHIP ASSIGNMENTS ** Actual User Assignments Assignments (if different) Node Name appleideinterface@6 A0 appleideinterface@5 A1 appleideinterface@14 A2 appleideinterface@43 A3 appleideinterface@15 A5 appleideinterface@38 A6 appleideinterface@13 A7 appleideinterface@12 A8 appleideinterface@11 A9 appleideinterface@8 A10 appleideinterface@35 -CS0 appleideinterface@20 -CS1 appleideinterface@18 DBUS245 appleideinterface@42 -DevSelect appleideinterface@22 -EEPROM_CE appleideinterface@19 -EEPROM_OE appleideinterface@31 -EEPROM_WE appleideinterface@40 -EEPROM_WP appleideinterface@30 -IORD appleideinterface@10 -I/OSelect appleideinterface@3 -I/OStrobe appleideinterface@2 -IOWR appleideinterface@27 LA0 appleideinterface@23 LA1 appleideinterface@21 LA2 appleideinterface@33 R_ATA appleideinterface@44 -R_HOST appleideinterface@39 R/W appleideinterface@25 -W_ATA appleideinterface@28 W_HOST appleideinterface@37 7Mclk Project Information d:\progs\cffa\pldlogic\version2.0dev\appleideinterface.rpt ** FILE HIERARCHY ** |appleidelogic:212| Device-Specific Information:d:\progs\cffa\pldlogic\version2.0dev\appleideinterface.rpt appleideinterface ***** Logic for device 'appleideinterface' compiled without errors. Device: EPM7032STC44-10 Device Options: Turbo Bit = OFF Security Bit = OFF Enable JTAG Support = ON User Code = ffff Device-Specific Information:d:\progs\cffa\pldlogic\version2.0dev\appleideinterface.rpt appleideinterface ** ERROR SUMMARY ** Info: Chip 'appleideinterface' in device 'EPM7032STC44-10' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device - - D E D e E E - v P B R S R U _ e O 7 G H l M M - O O e V _ R c G C U S A c C W / A l N S T T 3 t C P W 6 k D 0 1 -----------------------------------_ / 44 43 42 41 40 39 38 37 36 35 34 | #TDI | 1 33 | R_ATA -IOWR | 2 32 | #TDO -I/OStrobe | 3 31 | -EEPROM_WE GND | 4 30 | -IORD A1 | 5 29 | VCC A0 | 6 EPM7032STC44-10 28 | W_HOST #TMS | 7 27 | LA0 A10 | 8 26 | #TCK VCC | 9 25 | -W_ATA -I/OSelect | 10 24 | GND A9 | 11 23 | LA1 |_ 12 13 14 15 16 17 18 19 20 21 22 _| ------------------------------------ A A A A G V D - - L - 8 7 2 5 N C B E C A E D C U E S 2 E S P 1 P 2 R R 4 O O 5 M M _ _ O C E E N.C. = No Connect. This pin has no internal connection to the device. VCC = Dedicated power pin, which MUST be connected to VCC. GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. RESERVED = Unused I/O pin, which MUST be left unconnected. ^ = Dedicated configuration pin. + = Reserved configuration pin, which is tri-stated during user mode. * = Reserved configuration pin, which drives out in user mode. PDn = Power Down pin. @ = Special-purpose pin. # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use. & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. Device-Specific Information:d:\progs\cffa\pldlogic\version2.0dev\appleideinterface.rpt appleideinterface ** RESOURCE USAGE ** Shareable External Logic Array Block Logic Cells I/O Pins Expanders Interconnect A: LC1 - LC16 4/16( 25%) 16/16(100%) 0/16( 0%) 8/36( 22%) B: LC17 - LC32 16/16(100%) 16/16(100%) 2/16( 12%) 23/36( 63%) Total dedicated input pins used: 4/4 (100%) Total I/O pins used: 32/32 (100%) Total logic cells used: 20/32 ( 62%) Total shareable expanders used: 0/32 ( 0%) Total Turbo logic cells used: 0/32 ( 0%) Total shareable expanders not available (n/a): 2/32 ( 6%) Average fan-in: 5.30 Total fan-in: 106 Total input pins required: 16 Total fast input logic cells required: 0 Total output pins required: 16 Total bidirectional pins required: 0 Total reserved pins required 4 Total logic cells required: 20 Total flipflops required: 8 Total product terms required: 50 Total logic cells lending parallel expanders: 0 Total shareable expanders in database: 0 Synthesized logic cells: 0/ 32 ( 0%) Device-Specific Information:d:\progs\cffa\pldlogic\version2.0dev\appleideinterface.rpt appleideinterface ** INPUTS ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name 6 (8) (A) INPUT 0 0 0 0 0 2 0 A0 5 (7) (A) INPUT 0 0 0 0 0 2 0 A1 14 (15) (A) INPUT 0 0 0 0 0 2 0 A2 43 (2) (A) INPUT 0 0 0 0 0 1 1 A3 15 (16) (A) INPUT 0 0 0 0 0 1 0 A5 38 - - INPUT 0 0 0 0 0 1 0 A6 13 (14) (A) INPUT 0 0 0 0 0 1 0 A7 12 (13) (A) INPUT 0 0 0 0 0 1 0 A8 11 (12) (A) INPUT 0 0 0 0 0 1 0 A9 8 (10) (A) INPUT 0 0 0 0 0 1 0 A10 42 (1) (A) INPUT 0 0 0 0 0 11 3 -DevSelect 40 - - INPUT 0 0 0 0 0 2 0 -EEPROM_WP 10 (11) (A) INPUT 0 0 0 0 0 5 0 -I/OSelect 3 (6) (A) INPUT 0 0 0 0 0 4 0 -I/OStrobe 39 - - INPUT 0 0 0 0 0 11 0 R/W 37 - - INPUT G 0 0 0 0 0 0 0 7Mclk Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell G = Global Source. Fan-out destinations counted here do not include destinations that are driven using global routing resources. Refer to the Auto Global Signals, Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals Sections of this Report File for information on which signals' fan-outs are used as Clock, Clear, Preset, Output Enable, and synchronous Load signals. Device-Specific Information:d:\progs\cffa\pldlogic\version2.0dev\appleideinterface.rpt appleideinterface ** OUTPUTS ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name 35 17 B OUTPUT / 0 0 0 2 3 0 0 -CS0 20 30 B OUTPUT / 1 0 1 2 5 0 0 -CS1 18 32 B OUTPUT / 0 0 0 2 1 0 0 DBUS245 34 18 B FF + / 0 0 0 12 1 4 0 DEBUGOUT1 22 28 B OUTPUT / 0 0 0 4 1 1 0 -EEPROM_CE 19 31 B OUTPUT / 0 0 0 3 1 0 0 -EEPROM_OE 31 21 B OUTPUT / 1 0 1 4 1 0 0 -EEPROM_WE 30 22 B OUTPUT / 0 0 0 2 5 0 0 -IORD 2 5 A OUTPUT / 0 0 0 2 5 0 0 -IOWR 27 24 B FF + / 0 0 0 2 0 6 1 LA0 23 27 B FF + / 0 0 0 2 0 7 1 LA1 21 29 B FF + / 0 0 0 2 0 7 1 LA2 33 19 B OUTPUT / 0 0 0 2 5 0 0 R_ATA 44 3 A OUTPUT / 0 0 0 2 4 0 0 -R_HOST 25 26 B OUTPUT / 0 0 0 1 5 0 0 -W_ATA 28 23 B OUTPUT / 0 0 0 2 5 0 0 W_HOST Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell Device-Specific Information:d:\progs\cffa\pldlogic\version2.0dev\appleideinterface.rpt appleideinterface ** BURIED LOGIC ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name (26) 25 B TFFE + 0 0 0 1 5 2 1 |appleidelogic:212|CS_MASK (43) 2 A DFFE + 0 0 0 1 0 6 1 |appleidelogic:212|DelayDSEL1 (32) 20 B DFFE + 0 0 0 0 1 1 0 |appleidelogic:212|DelayDSEL2 (42) 1 A DFFE + 0 0 0 2 0 8 1 |appleidelogic:212|LA3 Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell Device-Specific Information:d:\progs\cffa\pldlogic\version2.0dev\appleideinterface.rpt appleideinterface ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'A': Logic cells placed in LAB 'A' +------- LC2 |appleidelogic:212|DelayDSEL1 | +----- LC1 |appleidelogic:212|LA3 | | +--- LC5 -IOWR | | | +- LC3 -R_HOST | | | | | | | | Other LABs fed by signals | | | | that feed LAB 'A' LC | | | | | A B | Logic cells that feed LAB 'A': LC1 -> - - * * | * * | <-- |appleidelogic:212|LA3 Pin 43 -> - * - - | * * | <-- A3 38 -> - - - - | - * | <-- A6 42 -> * * * * | * * | <-- -DevSelect 40 -> - - - - | - * | <-- -EEPROM_WP 39 -> - - * * | * * | <-- R/W 37 -> - - - - | - - | <-- 7Mclk LC20 -> - - * - | * - | <-- |appleidelogic:212|DelayDSEL2 LC24 -> - - * * | * * | <-- LA0 LC27 -> - - * * | * * | <-- LA1 LC29 -> - - * * | * * | <-- LA2 * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information:d:\progs\cffa\pldlogic\version2.0dev\appleideinterface.rpt appleideinterface ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'B': Logic cells placed in LAB 'B' +------------------------------- LC25 |appleidelogic:212|CS_MASK | +----------------------------- LC20 |appleidelogic:212|DelayDSEL2 | | +--------------------------- LC17 -CS0 | | | +------------------------- LC30 -CS1 | | | | +----------------------- LC32 DBUS245 | | | | | +--------------------- LC18 DEBUGOUT1 | | | | | | +------------------- LC28 -EEPROM_CE | | | | | | | +----------------- LC31 -EEPROM_OE | | | | | | | | +--------------- LC21 -EEPROM_WE | | | | | | | | | +------------- LC22 -IORD | | | | | | | | | | +----------- LC24 LA0 | | | | | | | | | | | +--------- LC27 LA1 | | | | | | | | | | | | +------- LC29 LA2 | | | | | | | | | | | | | +----- LC19 R_ATA | | | | | | | | | | | | | | +--- LC26 -W_ATA | | | | | | | | | | | | | | | +- LC23 W_HOST | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other LABs fed by signals | | | | | | | | | | | | | | | | that feed LAB 'B' LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B': LC25 -> * - * * - - - - - - - - - - - - | - * | <-- |appleidelogic:212|CS_MASK LC18 -> - - - - - * * * * - - - - - - - | - * | <-- DEBUGOUT1 LC28 -> - - - - * - - - - - - - - - - - | - * | <-- -EEPROM_CE LC24 -> * - - - - - - - - * - - - * * * | * * | <-- LA0 LC27 -> * - - * - - - - - * - - - * * * | * * | <-- LA1 LC29 -> * - - * - - - - - * - - - * * * | * * | <-- LA2 Pin 6 -> - - - - - * - - - - * - - - - - | - * | <-- A0 5 -> - - - - - * - - - - - * - - - - | - * | <-- A1 14 -> - - - - - * - - - - - - * - - - | - * | <-- A2 43 -> - - - - - * - - - - - - - - - - | * * | <-- A3 15 -> - - - - - * - - - - - - - - - - | - * | <-- A5 38 -> - - - - - * - - - - - - - - - - | - * | <-- A6 13 -> - - - - - * - - - - - - - - - - | - * | <-- A7 12 -> - - - - - * - - - - - - - - - - | - * | <-- A8 11 -> - - - - - * - - - - - - - - - - | - * | <-- A9 8 -> - - - - - * - - - - - - - - - - | - * | <-- A10 42 -> * - * * * - - - - * * * * * - * | * * | <-- -DevSelect 40 -> - - - - - - * - * - - - - - - - | - * | <-- -EEPROM_WP 10 -> - - - - * * * * * - - - - - - - | - * | <-- -I/OSelect 3 -> - - - - - * * * * - - - - - - - | - * | <-- -I/OStrobe 39 -> - - * * - - * * * * - - - * * * | * * | <-- R/W 37 -> - - - - - - - - - - - - - - - - | - - | <-- 7Mclk LC2 -> - * * * - - - - - * - - - * * * | - * | <-- |appleidelogic:212|DelayDSEL1 LC1 -> * - * * - - - - - * - - - * * * | * * | <-- |appleidelogic:212|LA3 * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information:d:\progs\cffa\pldlogic\version2.0dev\appleideinterface.rpt appleideinterface ** EQUATIONS ** A0 : INPUT; A1 : INPUT; A2 : INPUT; A3 : INPUT; A5 : INPUT; A6 : INPUT; A7 : INPUT; A8 : INPUT; A9 : INPUT; A10 : INPUT; R/W : INPUT; 7Mclk : INPUT; -DevSelect : INPUT; -EEPROM_WP : INPUT; -I/OSelect : INPUT; -I/OStrobe : INPUT; -- Node name is 'DBUS245' = '|appleidelogic:212|:172' from file "appleidelogic.tdf" line 134, column 32 -- Equation name is 'DBUS245', type is output DBUS245 = LCELL( _EQ001 $ GND); _EQ001 = -DevSelect & -EEPROM_CE & -I/OSelect; -- Node name is 'DEBUGOUT1' = '|appleidelogic:212|:72' from file "appleidelogic.tdf" line 77, column 13 -- Equation name is 'DEBUGOUT1', type is output DEBUGOUT1 = DFFE( _EQ002 $ GND, GLOBAL( 7Mclk), VCC, VCC, VCC); _EQ002 = A0 & A1 & A2 & A3 & A5 & A6 & A7 & A8 & A9 & A10 & !DEBUGOUT1 & !-I/OStrobe # DEBUGOUT1 & -I/OSelect; -- Node name is 'LA0' = '|appleidelogic:212|:68' from file "appleidelogic.tdf" line 71, column 9 -- Equation name is 'LA0', type is output LA0 = DFFE( A0 $ GND, GLOBAL( 7Mclk), VCC, VCC, -DevSelect); -- Node name is 'LA1' = '|appleidelogic:212|:69' from file "appleidelogic.tdf" line 72, column 9 -- Equation name is 'LA1', type is output LA1 = DFFE( A1 $ GND, GLOBAL( 7Mclk), VCC, VCC, -DevSelect); -- Node name is 'LA2' = '|appleidelogic:212|:70' from file "appleidelogic.tdf" line 73, column 9 -- Equation name is 'LA2', type is output LA2 = DFFE( A2 $ GND, GLOBAL( 7Mclk), VCC, VCC, -DevSelect); -- Node name is 'R_ATA' = '|appleidelogic:212|:142' from file "appleidelogic.tdf" line 121, column 62 -- Equation name is 'R_ATA', type is output R_ATA = LCELL( _EQ003 $ GND); _EQ003 = !-DevSelect & !LA0 & !LA1 & !LA2 & _LC001 & !_LC002 & R/W; -- Node name is 'W_HOST' = '|appleidelogic:212|:152' from file "appleidelogic.tdf" line 125, column 61 -- Equation name is 'W_HOST', type is output W_HOST = LCELL( _EQ004 $ GND); _EQ004 = !-DevSelect & !LA0 & !LA1 & !LA2 & !_LC001 & !_LC002 & !R/W; -- Node name is '|appleidelogic:212|CS_MASK' from file "appleidelogic.tdf" line 98, column 14 -- Equation name is '_LC025', type is buried _LC025 = TFFE( _EQ005, GLOBAL( 7Mclk), VCC, VCC, VCC); _EQ005 = !-DevSelect & LA0 & !LA1 & !LA2 & !_LC001 & !_LC025 # !-DevSelect & !LA0 & LA1 & !LA2 & !_LC001 & _LC025; -- Node name is '|appleidelogic:212|DelayDSEL1' from file "appleidelogic.tdf" line 109, column 15 -- Equation name is '_LC002', type is buried _LC002 = DFFE( -DevSelect $ GND, GLOBAL(!7Mclk), VCC, VCC, VCC); -- Node name is '|appleidelogic:212|DelayDSEL2' from file "appleidelogic.tdf" line 110, column 15 -- Equation name is '_LC020', type is buried _LC020 = DFFE( _LC002 $ GND, GLOBAL(!7Mclk), VCC, VCC, VCC); -- Node name is '|appleidelogic:212|LA3' from file "appleidelogic.tdf" line 74, column 9 -- Equation name is '_LC001', type is buried _LC001 = DFFE( A3 $ GND, GLOBAL( 7Mclk), VCC, VCC, -DevSelect); -- Node name is '-CS0' = '|appleidelogic:212|:163' from file "appleidelogic.tdf" line 132, column 39 -- Equation name is '-CS0', type is output -CS0 = LCELL( _EQ006 $ GND); _EQ006 = -DevSelect & _LC002 # _LC025 & R/W # !_LC001; -- Node name is '-CS1' = '|appleidelogic:212|:170' from file "appleidelogic.tdf" line 133, column 55 -- Equation name is '-CS1', type is output -CS1 = LCELL( _EQ007 $ GND); _EQ007 = -DevSelect & _LC002 # _LC025 & R/W # _LC001 # !LA2 # !LA1; -- Node name is '-EEPROM_CE' = '|appleidelogic:212|:83' from file "appleidelogic.tdf" line 83, column 39 -- Equation name is '-EEPROM_CE', type is output -EEPROM_CE = LCELL( _EQ008 $ GND); _EQ008 = !DEBUGOUT1 & !-I/OSelect & !-I/OStrobe # DEBUGOUT1 & -I/OSelect # -I/OSelect & -I/OStrobe # !-EEPROM_WP & !R/W; -- Node name is '-EEPROM_OE' = '|appleidelogic:212|:85' from file "appleidelogic.tdf" line 86, column 20 -- Equation name is '-EEPROM_OE', type is output -EEPROM_OE = LCELL( _EQ009 $ GND); _EQ009 = !DEBUGOUT1 & !-I/OSelect & !-I/OStrobe # DEBUGOUT1 & -I/OSelect # -I/OSelect & -I/OStrobe # !R/W; -- Node name is '-EEPROM_WE' = '|appleidelogic:212|:88' from file "appleidelogic.tdf" line 89, column 34 -- Equation name is '-EEPROM_WE', type is output -EEPROM_WE = LCELL( _EQ010 $ GND); _EQ010 = !DEBUGOUT1 & !-I/OSelect & !-I/OStrobe # DEBUGOUT1 & -I/OSelect # -I/OSelect & -I/OStrobe # R/W # !-EEPROM_WP; -- Node name is '-IORD' = '|appleidelogic:212|:113' from file "appleidelogic.tdf" line 112, column 37 -- Equation name is '-IORD', type is output -IORD = LCELL( _EQ011 $ GND); _EQ011 = !LA0 & !LA1 & !LA2 & !_LC001 # -DevSelect # !R/W # _LC002; -- Node name is '-IOWR' = '|appleidelogic:212|:105' from file "appleidelogic.tdf" line 111, column 37 -- Equation name is '-IOWR', type is output -IOWR = LCELL( _EQ012 $ GND); _EQ012 = !LA0 & !LA1 & !LA2 & !_LC001 # -DevSelect # R/W # _LC020; -- Node name is '-R_HOST' = '|appleidelogic:212|:131' from file "appleidelogic.tdf" line 118, column 43 -- Equation name is '-R_HOST', type is output -R_HOST = LCELL( VCC $ _EQ013); _EQ013 = !-DevSelect & !LA0 & !LA1 & !LA2 & !_LC001 & R/W; -- Node name is '-W_ATA' = '|appleidelogic:212|:158' from file "appleidelogic.tdf" line 129, column 49 -- Equation name is '-W_ATA', type is output -W_ATA = LCELL( VCC $ _EQ014); _EQ014 = !LA0 & !LA1 & !LA2 & _LC001 & !_LC002 & !R/W; -- Shareable expanders that are duplicated in multiple LABs: -- (none) Project Information d:\progs\cffa\pldlogic\version2.0dev\appleideinterface.rpt ** COMPILATION SETTINGS & TIMES ** Processing Menu Commands ------------------------ Design Doctor = off Logic Synthesis: Synthesis Type Used = Multi-Level Default Synthesis Style = NORMAL Logic option settings in 'NORMAL' style for 'MAX7000S' family DECOMPOSE_GATES = on DUPLICATE_LOGIC_EXTRACTION = on MINIMIZATION = part MULTI_LEVEL_FACTORING = on NOT_GATE_PUSH_BACK = on PARALLEL_EXPANDERS = off REDUCE_LOGIC = on REFACTORIZATION = on REGISTER_OPTIMIZATION = on RESYNTHESIZE_NETWORK = on SLOW_SLEW_RATE = on SOFT_BUFFER_INSERTION = on SUBFACTOR_EXTRACTION = on TURBO_BIT = off XOR_SYNTHESIS = on IGNORE_SOFT_BUFFERS = off USE_LPM_FOR_AHDL_OPERATORS = on Other logic synthesis settings: Automatic Global Clock = on Automatic Global Clear = on Automatic Global Preset = on Automatic Global Output Enable = on Automatic Fast I/O = off Automatic Register Packing = off Automatic Open-Drain Pins = on Automatic Implement in EAB = off One-Hot State Machine Encoding = off Optimize = 5 Default Timing Specifications: None Cut All Bidir Feedback Timing Paths = on Cut All Clear & Preset Timing Paths = on Ignore Timing Assignments = off Functional SNF Extractor = off Linked SNF Extractor = off Timing SNF Extractor = on Optimize Timing SNF = off Generate AHDL TDO File = off Fitter Settings = NORMAL Smart Recompile = off Total Recompile = off Interfaces Menu Commands ------------------------ EDIF Netlist Writer = off Verilog Netlist Writer = off VHDL Netlist Writer = off Compilation Times ----------------- Compiler Netlist Extractor 00:00:00 Database Builder 00:00:00 Logic Synthesizer 00:00:00 Partitioner 00:00:01 Fitter 00:00:00 Timing SNF Extractor 00:00:00 Assembler 00:00:02 -------------------------- -------- Total Time 00:00:03 Memory Allocated ----------------- Peak memory allocated during compilation = 4,475K