HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	appleidelogic.tdf
	{
		appleidelogic [USE_LPM_FOR_AHDL_OPERATORS] []
		{
			6 [USE_LPM_FOR_AHDL_OPERATORS=ON] [CS_MASK,NOT_RW,/EPROM_EN,C800_ACT,/DBUS245,/CS1,/CS0,/IORD,/IOWR,/W_ATA,W_HOST,R_ATA,/R_HOST,7Mclk,/IO_SEL,/IO_STRB,/DSEL,/RW,A10,A9,A8,A3,A2,A1,A0];
			4 [USE_LPM_FOR_AHDL_OPERATORS=ON] [/CFXX,/DBUS245,/CS1,/CS0,/IORD,/IOWR,/W_ATA,W_HOST,R_ATA,/R_HOST,7Mclk,/IO_SEL,/IO_STRB,/DSEL,/RW,A10,A9,A8,A3,A2,A1,A0];
			3 [USE_LPM_FOR_AHDL_OPERATORS=ON] [/CFXX,/DBUS245,/CS1,/IORD,/IOWR,/W_ATA,W_HOST,R_ATA,/R_HOST,/IO_SEL,/IO_STRB,/DSEL,/RW,A10,A9,A8,A3,A2,A1,A0];
			1 [USE_LPM_FOR_AHDL_OPERATORS=ON] [A0,A1,A2,A3,A8,A9,A10,/RW,/DSEL,/IO_STRB,/IO_SEL,/R_HOST,R_ATA,W_HOST,/W_ATA,/IOWR,/IORD,/CS0,/CS1,/DBUS245,/CFXX];
			5 [USE_LPM_FOR_AHDL_OPERATORS=ON] [A0,A1,A2,A3,A8,A9,A10,/RW,/DSEL,/IO_STRB,/IO_SEL,7Mclk,/R_HOST,R_ATA,W_HOST,/W_ATA,/IOWR,/IORD,/CS0,/CS1,/DBUS245,C800_ACT,/EPROM_EN,NOT_RW];
		}
	}
	nandltch.gdf
	{
		nandltch [] []
		{
			2 [] [];
		}
	}
	appleideinterface.gdf
	{
		appleideinterface [] []
		{
			0 [] [];
		}
	}
}
TREE
{
	appleideinterface::(0,0):(0): appleideinterface.gdf
	{
		appleidelogic:6:(0,0):(141): appleidelogic.tdf
		{
			nandltch:2:(48,12):(52): nandltch.gdf;
			nandltch:2:(65,13):(56): nandltch.gdf;
		}
	}
}