%-------------------------------------------------------------------
 CompactFlash/IDE Interface for the Apple II computer
 Project Home: http://dreher.net/CFforAppleII/
 Project Version 1.1   Dec 30, 2001

 Version 1.1  -  Fix for IDE drives /IORD & /IOWR timing
 Version 1.0  -  Initial Release

Note: Remember that the Apple II Bus does not have Phase 2!
--------------------------------------------------------------------%
FUNCTION nandltch (sn, rn) RETURNS (q);
FUNCTION DFF (D, CLK) RETURNS (Q);

SUBDESIGN AppleIDELogic
(
	A0, A1, A2, A3, A8, A9, A10 			: INPUT;
	/RW, /DSEL, /IO_STRB, /IO_SEL           : INPUT;
	7Mclk                                   : INPUT;
						
	/R_HOST, R_ATA, W_HOST, /W_ATA          : OUTPUT;
	/IOWR, /IORD, /CS0, /CS1                : OUTPUT;
	/DBUS245, /CFXX                         : OUTPUT;
)
VARIABLE
SET_MASK, RESET_MASK, CS_MASK, DelayDSEL	: NODE;

BEGIN
   DEFAULTS
	CS_MASK = GND;	
   END DEFAULTS;

%-----------------------------------------------------------------------------------------%
% Fix for SanDisk Family of CompactFlash drives. True IDEmode is not quite True!          %	
% The idea here is to mask the read cycle the preceeds all write cycles, because the read %
% cycle was confusing the Sandisk  %

	SET_MASK	= /DSEL # (A3 # A2 # A1 # !A0);
	RESET_MASK	= /DSEL # (A3 # A2 # !A1 # A0);
	CS_MASK		= nandltch(SET_MASK, RESET_MASK);
%-----------------------------------------------------------------------------------------%

% ------ Delay /IORD and /IOWR approx 50ns using a D type FF and the Apple Bus 7Mhz clock %
% the A0-A3 signals are used to keep from generating these signals when accessing the latches %
	DelayDSEL	= DFF(/DSEL, 7Mclk);
	/IOWR		= /DSEL # DelayDSEL # /RW  # !(A3 # A2 # A1 # A0);
	/IORD		= /DSEL # DelayDSEL # !/RW # !(A3 # A2 # A1 # A0);

% decode address range $CFxx for deselecting the onboard EPROM %
	/CFXX 		= !(A8 & A9 & A10 & !/IO_STRB);

% Latch chip select logic %
	/R_HOST 	= /DSEL # A3 # A2 # A1 # A0 # !/RW;
	 R_ATA 		= !/DSEL & (A3 # (A2 & A1)) & /RW;
	 W_HOST 	= !/DSEL & !(A3 # A2 # A1 # A0) & !/RW;
	/W_ATA 		= /DSEL # !(A3 # (A2 & A1)) # /RW;

% device chip select logic % 
	/CS0 		= /DSEL # !A3 # (CS_MASK & /RW);
	/CS1 		= /DSEL # (A3 # !(A1 & A2)) # (CS_MASK & /RW);
	/DBUS245	= /DSEL & /IO_STRB & /IO_SEL;

END;